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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00497 rev. *e revised june 29, 2016 s25FL116K, s25fl132k, s25fl164k 16 mbit (2 mbyte), 32 mbit (4 mbyte), 64 mbit (8 mbyte) 3.0v spi flash memory features ? serial peripheral interface (spi) with multi-i/o ? spi clock polarity and phase modes 0 and 3 ? command subset and footprint compatible with s25fl-k ? read ? normal read (serial): ? 50 mhz clock rate ( ? 40 c to +85 c/105 c) ? 45 mhz clock rate ( ? 40 c to +125 c) ? fast read (serial): ? 108 mhz clock rate ( ? 40 c to +85 c/105 c) ? 97 mhz clock rate ( ? 40 c to +125 c) ? dual read: ? 108 mhz clock rate ( ? 40 c to +85 c/105 c) ? 97 mhz clock rate ( ? 40 c to +125 c) ? quad read: ? 108 mhz clock rate ( ? 40 c to +85 c/105 c) ? 97 mhz clock rate for s25fl164k ( ? 40 c to +125 c) ? 54 mb/s maximum continuous data transfer rate ( ? 40 c to +85 c/105 c) ? efficient execute-in-place (xip) ? continuous and wrapped read modes ? serial flash discover able parameters (sfdp) ? program ? serial-input page program (up to 256 bytes) ? program suspend and resume ? erase ? uniform sector erase (4 kb) ? uniform block erase (64 kb) ? chip erase ? erase suspend and resume ? cycling endurance ? 100k program-erase cycles on any sector ? data retention ? 20-year data retention ? security ? three 256-byte security r egisters with otp protection ? low supply voltage protection of the entire memory ? pointer-based security protection feature ( s25fl132k and s25fl164k ) ? top / bottom relative block protection range, 4 kb to all of memory ? 8-byte unique id for each device ? non-volatile status register bits control protection modes ? software command protection ? hardware input signal protection ? lock-down until power cycle protection ? otp protection of security registers ? 90 nm floating gate technology ? single supply voltage ? 2.7 v to 3.6 v (industrial, industrial plus, and extended temperature range) ? 2.6 v to 3.6 v (extended temperature range) ? temperature ranges ? industrial ( ? 40 c to +85 c) ? industrial plus ( ? 40 c to +105 c) ? extended ( ? 40 c to +125 c) ? industrial, gt grade, aec-q100 grade 3 ( ? 40 c to +85 c) ? industrial plus, gt grade, aec-q100 grade 2( ? 40 c to +105 c) ? extended, gt grade, aec-q100 grade 1 ( ? 40 c to +125 c) ? package options ? s25FL116K ? 8-lead soic (150 mil) ? soa008 ? 8-lead soic (208 mil) ? soc008 ? 8-contact wson 5 mm x 6 mm ? wnd008 ? 24-ball bga 6 mm ? 8 mm ? fab024 and fac024 ?kgd / kgw ? s25fl132k ? 8-lead soic (150 mil) ? soa008 ? 8-lead soic (208 mil) ? soc008 ? 8-contact uson 4 mm ? 4 mm ? unf008 ? 8-contact wson 5 mm ? 6 mm ? wnd008 ? 24-ball bga 6 mm ? 8 mm ? fab024 and fac024 ?kgd / kgw ? s25fl164k ? 8-lead soic (208 mil) ? soc008 ? 16-lead soic (300 mil) ? so3016 ? 8-contact wson 5 mm ? 6 mm ? wnd008 ? 24-ball bga 6 mm ? 8 mm ? fab024 and fac024 ?kgd / kgw
document number: 002-00497 rev. *e page 2 of 90 s25FL116K, s25fl132k, s25fl164k logic block diagram performance summary maximum read rates (v cc = 2.7 v to 3.6 v, 85 c/105 c) command clock rate (mhz) mbytes/s read 50 6.25 fast read 108 13.5 dual read 108 27 quad read 108 54 typical program and erase rates (v cc = 2.7 v to 3.6 v, 85 c/105 c) operation kbytes/s page programming (256-byte page buffer) 365 4-kbyte sector erase 81 64-kbyte sector erase 131 typical current consumption (v cc = 2.7 v to 3.6 v, 85 c/105 c) operation current (ma) serial read 50 mhz 7 serial read 108 mhz 12 dual read 108 mhz 14 quad read 108 mhz 16 program 20 erase 20 standby 0.015 deep-power down 0.002 memory control logic data path x decoders cs# sck si/io0 so/io1 hold#/io3 wp#/io2 i/o y decoders data latch
document number: 002-00497 rev. *e page 3 of 90 s25FL116K, s25f l132k, s25fl164k contents 1. general description ..................................................... 4 1.1 migration notes.............................................................. 5 1.2 glossary......................................................................... 6 1.3 other resources............................................................ 7 hardware interface 2. signal descriptions ..................................................... 8 2.1 input / output summary................................................. 8 2.2 address and data configuratio n.................................... 9 2.3 serial clock (sck) ......................................................... 9 2.4 chip select (cs#) .......................................................... 9 2.5 serial input (si) / io0 ..................................................... 9 2.6 serial output (so) / io1................................................. 9 2.7 write protect (wp#) / io2 .............................................. 9 2.8 hold# / io3 ................................................................ 10 2.9 core and i/o signal voltage supply (v cc ) .................. 10 2.10 supply and signal ground (v ss ) ................................. 10 2.11 not connected (nc) .................................................... 10 2.12 reserved for future use (rfu )................................... 10 2.13 do not use (dnu) ................. .............. .............. .......... 11 2.14 block diagrams............................................................ 11 3. signal protocols ......................................................... 12 3.1 spi clock modes ......................................................... 12 3.2 command protocol ...................................................... 12 3.3 interface states............................................................ 16 3.4 status register effects on the interface ...................... 19 3.5 data protection ............................................................ 19 4. electrical characteristics .......................................... 20 4.1 absolute maximum ratings ...... ................................... 20 4.2 thermal resistance ..................................................... 21 4.3 operating ranges........................................................ 21 4.4 dc electrical characteristic s ....................................... 22 4.5 ac measurement conditions .... .............. .............. ....... 23 4.6 power-up timing ......................................................... 24 4.7 power-on (cold) reset................................................ 25 4.8 ac electrical characteristics. ........................................ 25 5. physical interface ....................................................... 30 5.1 connection diagrams ............. ............... .............. ......... 30 5.2 physical diagrams ........................................................ 32 software interface 6. address space maps .................................................. 39 6.1 overview....................................................................... 39 6.2 flash memory array...................................................... 39 6.3 security registers......................................................... 40 6.4 security register 0 ? serial flash discoverable parameters (sfdp ? jedec jesd216b) ...... .............. ........... ....... 40 6.5 status registers ........................................................... 50 6.6 device identification.............. ........... ........... ........... ....... 60 7. functional description ............................................... 61 7.1 spi operations ............................................................. 61 7.2 write protection ............................................................ 62 7.3 status registers ........................................................... 62 8. commands .................................................................. 63 8.1 configuration and status commands ........................... 65 8.2 program and erase commands ................................... 68 8.3 read commands ...... .............. ............... .............. ......... 71 8.4 reset commands ......................................................... 76 8.5 id and security commands .......................................... 77 8.6 set block / pointer protection (39h) ? s25fl132k and s25fl164k.......................... 82 9. data integrity ............................................................... 84 9.1 erase endurance .......................................................... 84 9.2 data retention .............................................................. 84 9.3 initial delivery state ...................................................... 84 10. ordering information .................................................. 85 11. revision history .......................................................... 89
document number: 002-00497 rev. *e page 4 of 90 s25FL116K, s25fl132k, s25fl164k 1. general description the s25fl1-k of non-volatile flash memory devices connect to a host system via a serial peripheral interface (spi). traditional spi single bit serial input and output (single i/o or sio) is sup ported as well as optional two bit (dual i/o or dio) and four bit (quad i/o or qio) serial protocols. this multiple wi dth interface is called spi multi-i/o or mio. the spi-mio protocols use only 4 to 6 signals: ? chip select (cs#) ? serial clock (sck) ? serial data ? io0 (si) ? io1 (so) ? io2 (wp#) ? io3 (hold#) the sio protocol uses serial input (si) and serial output (so) for data transfer. the dio protocols use io0 and io1 to input or output two bits of data in each clock cycle. the write protect (wp#) input signal option allows hardware cont rol over data protection. software controlled commands can also manage data protection. the hold# input signal option allows commands to be suspended and resumed on any clock cycle. the qio protocols use all of the data signal s (io0 to io3) to transfer 4 bits in eac h clock cycle. when the qio protocols are e nabled the wp# and hold# inputs a nd features are disabled. clock frequency of up to 108 mhz is suppor ted, allowing data transfer rates up to: ? single bit data path = 13.5 mbytes/s ? dual bit data path = 27 mbytes/s ? quad bit data path = 54 mbytes/s executing code directly from flash memory is often called execute-in-place or xip. by using s25fl1-k devices at the higher cloc k rates supported, with qio commands, the command read transfer rate can match or exceed traditional x8 or x16 parallel interface , asynchronous, nor flash memories, while reducing signal count dramatically. the continuous read mode allows for random memory access with as few as 8-clocks of overhead for each a ccess, providing efficient xip operation. the wrapped read mode provides efficient instruction or data cache refill via a fast r ead of the critical byte that causes a cache miss, followed by reading all other bytes in the same cache line in a single read command. the s25fl1-k: ? support jedec standard manufacture r and device type identification. ? program pages of 256 bytes each. one to 256 bytes can be programmed in each page program operation. pages can be erased in groups of 16 (4-kb aligned sector erase), groups of 256 (64-kb aligned blo ck erase), or the entire chip (chip erase). ? the s25fl1-k devices operate on a single 2.6v/2.7v to 3.6v power supply and all devices are offered in space-saving packages. ? provides an ideal storage solution for s ystems with limited space, signal connect ions, and power. these memories offer flexibility and performance well beyond ordinary serial flash de vices. they are ideal for code shadowing to ram, executing code directly (xip), and storing reprogrammable data.
document number: 002-00497 rev. *e page 5 of 90 s25FL116K, s25fl132k, s25fl164k 1.1 migration notes 1.1.1 features comparison the s25fl1-k is command set and footprint compatible with prior generation fl-k and fl-p families. notes: 1. s25fl-k family devices can erase 4-kb sectors in groups of 32 kb or 64 kb. 2. s25fl1-k family devices can erase 4-kb sectors in groups of 64 kb. 3. s25fl-p has either 64-kb or 256-kb uniform sectors depending on an ordering option. 4. refer to individual data sheets for further details. 1.1.2 known feature differen ces from prior generations 1.1.2.1 secure silicon region (otp) the size and format (address map) of the one time program area is the same for the s25fl1-k and the s25fl-k but different for the s25fl-p. table 1.1 fl generations comparison parameter s25fl1-k s25fl-k s25fl-p technology node 90 nm 90 nm 90 nm architecture floating gate floating gate mirrorbit ? release date in production in production in production density 16 mbit - 64 mbit 4 mbit - 128 mbit 32 mbit - 256 mbit bus width x1, x2, x4 x1, x2, x4 x1, x2, x4 supply voltage 2.6v / 2.7v - 3. 6v 2.7v - 3.6v 2.7v - 3.6v normal read speed 6 mb/s (50 mhz) 5.4 mb/s (45 mhz for 125c) 6 mb/s (50 mhz) 5 mb/s (40 mhz) fast read speed 13.5 mb/s (108 mhz) 12.12 mb/s (97 mhz for 125c) 13 mb/s (104 mhz) 13 mb/s (104 mhz) dual read speed 27 mb/s (108 mhz) 24.25 mb/s (97 mhz for 125c) 26 mb/s (104 mhz) 20 mb/s (80 mhz) quad read speed 54 mb/s (108 mhz at 85c/105c) 48.5 mb/s (97 mhz at 125c) 52 mb/s (104 mhz) 40 mb/s (80 mhz) program buffer size 256b 256b 256b page programming time (typ.) 700 s (256b) 700 s (256b) 1500 s (256b) program suspend / resume yes yes no erase sector size 4 kb / 64 kb 4 kb / 32 kb / 64 kb 64 kb / 256 kb parameter sector size n/a n/a 4 kb sector erase time (typ.) 50 ms (4 kb), 500 ms (64 kb) 30 ms (4 kb), 150 ms (64 kb) 500 ms (64 kb) erase suspend / resume yes yes no otp size 768b (3 x 256b) 768b (3 x 256b) 506b operating temperature -40c to +85c / +105c / +125c -40c to +85c -40c to +85c / +105c
document number: 002-00497 rev. *e page 6 of 90 s25FL116K, s25fl132k, s25fl164k 1.1.2.2 commands not supported the following s25fl-k and s25fl-p commands are not supported: ? quad page pgm (32h) ? half-block erase 32k (52h) ? word read quad i/o (e7) ? octal word read quad i/o (e3h) ? mfid dual i/o (92h) ? mfid quad i/o (94h) ? read unique id (4bh) 1.1.2.3 new features the s25fl1-k introduces new features to low density spi category memories: ? variable read latency (number of dummy cycles) for faster initial access time or higher clock rate read commands ? industrial plus and ex tended temperature range ? volatile configuration option in additi on to legacy non-volatile configuration 1.2 glossary ? command. all information transferred between t he host system and memory dur ing one period while cs# is low. this includes the instruction (sometimes called an oper ation code or opcode) and any required address, mode bits, latency cycles, or data. ? flash . the name for a type of electrical erase programmable read only memory (eeprom) that erases large blocks of memory bits in parallel, making the erase operation much faster than early eeprom. ? high . a signal voltage level v ih or a logic level representing a binary one (1). ? instruction . the 8-bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). the instruction is always the first 8 bits transf erred from host system to the memory in any command. ? low . a signal voltage level ? v il or a logic level representing a binary zero (0). ? lsb . least significant bit. generally the right most bit, with the lo west order of magnitude value, within a group of bits of a register or data value. ? msb . most significant bit. generally the left most bit, with the highest order of magnitu de value, within a group of bits of a register or data value. ? non-volatile . no power is needed to maintain data stored in the memory. ? opn . ordering part number. the alphanumeric string specifying th e memory device type, density, package, factory non-volatile configuration, etc. used to select the desired device. ? page . 256-byte aligned and length group of data. ? pcb . printed circuit board. ? register bit references . are in the format: register_name[bit_number] or register_name[bit_range_msb: bit_range_lsb]. ? sector . erase unit size; all sectors are physically 4-kbytes al igned and length. depending on the erase command used, groups of physical sectors may be erased as a larger logical sector of 64 kbytes. ? write . an operation that changes data within volatile or non-volati le registers bits or non-volatile flash memory. when changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in t he same way that volatile data is modified ? as a single operatio n. the non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data.
document number: 002-00497 rev. *e page 7 of 90 s25FL116K, s25fl132k, s25fl164k 1.3 other resources 1.3.1 cypress flash memory roadmap http://www.cypress. com/flash-roadmap 1.3.2 links to software http://www.cypress. com/spansionsupport 1.3.3 links to application notes http://www.cypress.com/spansionappnotes
document number: 002-00497 rev. *e page 8 of 90 s25FL116K, s25fl132k, s25fl164k hardware interface serial peripheral interface with multiple input / output (spi-mio) many memory devices connect to their host system with separate pa rallel control, address, and data signals that require a large number of signal connections and larger package size. the large number of connections increase power consumption due to so many signals switching and the la rger package increases cost. the s25fl1-k reduces the number of signals for connection to the host system by serially transferring all control, address, and data information over 4 to 6 signals. this reduces the cost of the memory package, reduces signal switching power, and either reduce s the host connection count or frees host con nectors for use in providing other features. the s25fl1-k uses the industry standard single bit serial peri pheral interface (spi) and also supports commands for two bit (du al) and four bit (quad) wide serial transfers. this multip le width interface is called spi multi-i/o or spi-mio. 2. signal descriptions 2.1 input / output summary note: 1. a signal name ending with the # symbol is active when low. table 2.1 signal list signal name type description sck input serial clock. cs# input chip select. si (io0) i/o serial input for single bit data commands. io0 for dual or quad commands. so (io1) i/o serial output for single bit data commands. io1 for dual or quad commands. wp# (io2) i/o write protect in single bit or dual data commands. io2 in quad mode. the signal has an internal pull-up resistor and may be left uncon nected in the host system if not used for quad commands. hold# (io3) i/o hold (pause) serial transfer in single bit or dual data commands. io3 in quad-i/o mode. the signal has an internal pull-up resistor and may be left unconnected in the host system if not used for quad commands. v cc supply core and i/o power supply. v ss supply ground. nc unused not connected. no device internal signal is connecte d to the package connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). however, any signal connected to an nc must not have voltage levels higher than v cc . rfu reserved reserved for future use. no device internal signal is cu rrently connected to the package connector but there is potential future use of th e connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of future enhanced features in compatible footprint devices. dnu reserved do not use. a device internal signal may be connected to the package connector. the connection may be used by spansion ? for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when the signal is at v il . the signal has an internal pull-down resi stor and may be left unconnected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to this connection.
document number: 002-00497 rev. *e page 9 of 90 s25FL116K, s25fl132k, s25fl164k 2.2 address and data configuration traditional spi single bit wide commands (single or sio) send in formation from the host to the memory only on the si signal. da ta may be sent back to the ho st serially on the serial output (so) signal. dual or quad output commands send information from the host to the memory only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or fo ur bit (nibble) groups on io0, io1, io2 , and io3. dual or quad input / output (i/o ) commands send information from the host to the memory as bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io 2, and io3. data is returned to the host simila rly as bit pairs on io0 and io1 or four bit (nibb le) groups on io0, io1, io2, and io3. 2.3 serial clock (sck) this input signal provides the synchronization reference for the spi interface. instructions, add resses, or data input are latc hed on the rising edge of the sck signal. data output changes after the falling edge of sck. 2.4 chip select (cs#) the chip select signal indicates when a command for the device is in process and the other sig nals are relevant for the memory device. when the cs# signal is at the logic high state, the dev ice is not selected and all input signals are ignored and all ou tput signals are high impedance. unless an internal program, erase or write status registers embedded operation is in progress, the device will be in the standby power mode. driving the cs# input to logic low state enables the de vice, placing it in the active power mode. after power-up, a falling edge on cs# is required prior to the start of any command. 2.5 serial input (si) / io0 this input signal is used to tr ansfer data serially into the de vice. it receives instructions, a ddresses, and data to be progra mmed. values are latched on the rising edge of serial sck clock signal. si becomes io0 - an input and output during dual and quad comm ands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock sig nal) as well as shifting out data (on the falling edge of sck) . 2.6 serial output (so) / io1 this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of the serial s ck clock signal. so becomes io1, an input and output during dual and quad commands for receiv ing instructions, addresses, and data to be programmed (values latched on rising edge of serial sck clock sig nal) as well as shifting out data (on the falling edge of sck) . 2.7 write protect (wp#) / io2 when wp# is driven low (v il ), while the status register prot ect bits (srp1 and srp0) of the st atus registers (sr2[0] and sr1[7]) are set to 0 and 1 respectively, it is not possible to write to th e status registers. this preven ts any alteration of the statu s registers. as a consequence, all the data bytes in t he memory area that are protec ted by the block protect, tb, sec, and cmp bits in the status registers, are also hardw are protected against data modification while wp# remains low. the wp# function is not available when the quad mode is enable d (qe) in status register-2 (sr2[1]=1). the wp# function is replaced by io2 for input and output during quad mode for rece iving addresses, and data to be programmed (values are latched on rising edge of the sck signal) as well as sh ifting out data (on the falling edge of sck). wp# has an internal pull-up resistance; when unconnected, wp# is at v ih and may be left unconnected in the host system if not used for quad mode.
document number: 002-00497 rev. *e page 10 of 90 s25FL116K, s25fl132k, s25fl164k 2.8 hold# / io3 the hold# signal is used to pause any serial communications with the device without deselecting the device or stopping the seri al clock. to enter the hold condition, the device must be selected by driv ing the cs# input to the logic low state. it is required that t he user keep the cs# input low state during the entire duration of the hold condition. this is to ensure that the state of the interfac e logic remains unchanged from the moment of entering the hold condition. the hold condition starts on the falling edge of the hold (hold#) signal, provided that this coincides with sck being at the lo gic low state. if the falling edge does not coincide with the sck signal bei ng at the logic low state, the hold condition starts whenev er the sck signal reaches the logic low state. taking the hold# signal to the logic low state does not terminate any write, program or erase operation that is currently in progress. during the hold condition, so is in high impedance and both the si and sck input are don't care. the hold condition ends on the rising edge of the hold (hold#) si gnal, provided that this coincides with the sck signal being a t the logic low state. if the rising edge does not coincide with the sck signal being at the logic low state, the hold condition ends whenever the sck signal reaches the logic low state. figure 2.1 hold condition 2.9 core and i/o signal voltage supply (v cc ) v cc is the voltage source for all device internal logic and input / output signals. it is the single voltage used for all device f unctions including read, program, and erase. 2.10 supply and signal ground (v ss ) v ss is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers. 2.11 not connected (nc) no device internal signal is connected to the package connector no r is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). 2.12 reserved for future use (rfu) no device internal signal is currently connected to the package connector but is ther e potential future use for the connector f or a signal. it is recommended to not use rfu connectors for pcb r outing channels so that the pcb may take advantage of future enhanced features in com patible footprint devices. cs# sck hold# si_or_io_(during_input) so_or_io_(internal) so_or_io_(external) valid input don?t care valid input don?t care valid input a b c d e a b b c d e hold condition standard use hold condition non-standard use
document number: 002-00497 rev. *e page 11 of 90 s25FL116K, s25fl132k, s25fl164k 2.13 do not use (dnu) a device internal signal may be connected to the package connecto r. the connection may be used by cypress for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inactive when th e signal is at v il . the signal has an inte rnal pull-down resistor and may be left unconnected in t he host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. 2.14 block diagrams figure 2.2 bus master and memory devices on the spi bus ? single bit data path figure 2.3 bus master and memory devices on the spi bus ? dual bit data path figure 2.4 bus master and memory devices on the spi bus ? quad bit data path spi bus master hold# wp# si so sck cs2# cs1# spi flash spi flash hold# wp# so si sck cs2# cs1# spi bus master hold# wp# io1 io0 sck cs2# cs1# spi flash spi flash hold# wp# io0 io1 sck cs2# cs1# spi bus master io3 io2 io1 io0 sck cs2# cs1# spi flash spi flash io3 io2 io0 io1 sck cs2# cs1#
document number: 002-00497 rev. *e page 12 of 90 s25FL116K, s25fl132k, s25fl164k 3. signal protocols 3.1 spi clock modes the s25fl1-k can be driven by an embedded microcontroller (b us master) in either of the two following clocking modes. ? mode 0 with clock polarity (cpol) = 0 and, clock phase (cpha) = 0 ? mode 3 with cpol = 1 and, cpha = 1 for these two modes, input data into the device is always latched in on the rising edge of the sck signal and the output data i s always available from the falling edge of the sck clock signal. the difference between the two modes is t he clock polarity when the bus master is in standby mode and not transferring any data . ? sck will stay at logic low state with cpol = 0, cpha = 0 ? sck will stay at logic high state with cpol = 1, cpha = 1 figure 3.1 spi modes supported timing diagrams throughout the remainder of the document are g enerally shown as both mode 0 and 3 by showing sck as both high and low at the fall of cs#. in some cases a timing diagram ma y show only mode 0 with sck low at the fall of cs#. in such a case, mode 3 timing simply means clock is high at the fall of cs# so no sck rising edge set up or hold time to the falling edge of cs# is needed for mode 3. sck cycles are measured (counted) from one falling edge of sc k to the next falling edge of sck. in mode 0 the beginning of the first sck cycle in a command is measured from the falling edge of cs# to the first falling edge of sck because sck is already l ow at the beginning of a command. 3.2 command protocol all communication between the host system and s25fl1-k me mory devices is in the form of units called commands. all commands begin with an instruction that selects the type of information transfer or device operation to be performed. comma nds may also have an address, instruction modifier (mode), latency pe riod, data transfer to the memory, or data transfer from the memory. all instruction, address, and data information is tr ansferred serially between the host system and memory device. all instructions are transferred from host to memory as a single bit serial sequence on the si signal. single bit wide commands may provide an address or data sent only on the si signal. data may be sent back to the host serially on the so signal. dual or quad output commands provide an address sent to the memo ry only on the si signal. data will be returned to the host as a sequence of bit pairs on io0 and io1 or four bit (nibble) groups on io0, io1, io2, and io3. dual or quad input / output (i/o ) commands provide an address sent from the host as bit pairs on io0 and io1 or, four bit (nibb le) groups on io0, io1, io2, and io3. data is returned to the host similarly as bit pairs on io0 and io1 or, four bit (nibble) grou ps on io0, io1, io2, and io3. cpol=0_cpha=0_sck cpol=1_cpha=1_sck cs# si so msb msb
document number: 002-00497 rev. *e page 13 of 90 s25FL116K, s25fl132k, s25fl164k commands are structured as follows: ? each command begins with cs# going low and ends with cs# return ing high. the memory device is selected by the host driving the chip select (cs#) signal low throughout a command. ? the serial clock (sck) marks the transfer of each bit or group of bits between the host and memory. ? each command begins with an eight bit (byte) instruction. the instruction is always presented only as a single bit serial sequence on the serial input (si) signal with one bit transferred to the memory device on each sck rising edge. the instruction selects the type of information transfe r or device operation to be performed. ? the instruction may be stand alone or may be followed by address bits to select a location within one of several address spaces in the device. the instruction determines the address space used. the address is a 24-bit, byte boundary, address. the address transfers occur on sck rising edge. ? the width of all transfers following the in struction are determined by the instruction sent. follo wing transfers may continue t o be single bit serial on only the si or serial output (so) signals, they may be done in 2-bit groups per (dual) transfer on the io0 and io1 signals, or they may be done in 4-bit groups per (quad) transfer on the io0-io3 signals. within the dual or quad groups the least significant bit is on io0. more significant bits are plac ed in significance order on each higher numbered io signal. sing le bits or parallel bit groups are transferred in most to least significant bit order. ? some instructions send an instruction modi fier called mode bits, following the address, to indicate that the next command will be of the same type with an implied, rather than an explicit, instruction. the next comm and thus does not provide an instruction byte, only a new address and mode bits. this reduces the time needed to send each command when the same command type is repeated in a sequence of commands. the mode bit transfers occur on sck rising edge. ? the address or mode bits may be followed by write data to be stored in the memory device or by a read latency period before read data is returned to the host. ? write data bit transfers occur on sck rising edge. ? sck continues to toggle during any read access latency period. the latency may be zero to several sck cycles (also referred to as dummy cycles). at the end of the read latency cycles, the first read data bits are driven from the outputs on sck falling edge at the end of the last re ad latency cycle. the firs t read data bits are considered transf erred to the host on the followin g sck rising edge. each following transfer occurs on the next sck rising edge. ? if the command returns read data to the host , the device continues sending data transfers until the host takes the cs# signal high. the cs# signal can be driven high after any transfer in the read data sequence. th is will terminate the command. ? at the end of a command that does not return data, the host dr ives the cs# input high. the cs# signal must go high after the eighth bit, of a stand alone instruction or, of the last write dat a byte that is transferred. that is, the cs# signal must be d riven high when the number of clock cycles after cs# signal was driven lo w is an exact multiple of eight cycles. if the cs# signal do es not go high exactly at the eight sck cycle boundary of the instru ction or write data, the command is rejected and not executed. ? all instruction, address, and mode bits are shifted into the device with the most signi ficant bits (msb) first. the data bits a re shifted in and out of the device msb first. all data is transf erred in byte units with the lowest address byte sent first. foll owing bytes of data are sent in lowest to highest byte address order i.e. the byte address increments. ? all attempts to read the flash memory array during a program, erase, or a write cycle (embedded operations) are ignored. the embedded operation will continue to execut e without any affect. a very limited set of commands are accepted during an embedded operation. these are discussed in the individual command descriptions. ? depending on the command, the time for execution varies. a co mmand to read status information from an executing command is available to determine when the command complete s execution and whether the command was successful.
document number: 002-00497 rev. *e page 14 of 90 s25FL116K, s25fl132k, s25fl164k 3.2.1 command sequence examples figure 3.2 stand alone instruction command figure 3.3 single bit wide input command figure 3.4 single bit wide output command figure 3.5 single bit wide i/o command without latency figure 3.6 single bit wide i/o command with latency cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input data cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data 2 cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data 2 cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
document number: 002-00497 rev. *e page 15 of 90 s25FL116K, s25fl132k, s25fl164k figure 3.7 dual output command figure 3.8 quad output command without latency figure 3.9 dual i/o command figure 3.10 quad i/o command additional sequence diagrams, specific to each command, are provided in commands on page 63 . cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 23 22 21 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction dummy data 1 data 2 address cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 23 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address data 1 data 2 data 3 data 4 data 5 ... cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 22 2 0 6 4 2 0 6 4 2 0 23 3 1 7 5 3 1 7 5 3 1 instruction address dummy data 1 data 2 cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 4 0 4 4 0 4 0 4 0 4 0 21 5 1 5 5 1 5 1 5 1 5 1 22 6 2 6 6 2 6 2 6 2 6 2 23 7 3 7 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4
document number: 002-00497 rev. *e page 16 of 90 s25FL116K, s25fl132k, s25fl164k 3.3 interface states this section describes the input and output signal levels as related to the spi interface behavior. legend: z = no driver - floating signal hl = host driving v il hh = host driving v ih hv = either hl or hh x = hl or hh or z ht = toggling between hl and hh ml = memory driving v il mh = memory driving v ih mv = either ml or mh 3.3.1 low power hardware data protection when v cc is less than v wi the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range. 3.3.2 power-on (cold) reset when the core voltage supply remains at or below the v cc (low) voltage for > t pd time, then rises to v wi the device will begin its power-on-reset (por) process. por continue s until the end of t puw . during t puw the device does not react to write commands. following the end of t puw the device transitions to the interfac e standby state and can accept write commands. for additional information on por see power-on (cold) reset on page 25 . table 3.1 interface states summary interface state v cc sck cs# hold# / io3 wp# / io2 so / io1 si / io0 low power hardware data protection < v wi xxxxzx power-on (cold) reset v cc (min) x hh x x z x interface standby v cc (min) x x x x z x instruction cycle v cc (min) ht hl hh hv z hv hold cycle v cc (min) hv or ht hl hl x x x single input cycle host to memory transfer v cc (min) ht hl hh x z hv single latency (dummy) cycle v cc (min) ht hl hh x z x single output cycle memory to host transfer v cc (min) ht hl hh x mv x dual input cycle host to memory transfer v cc (min) ht hl hh x hv hv dual latency (dummy) cycle v cc (min) ht hl hh x x x dual output cycle memory to host transfer v cc (min) ht hl hh x mv mv quad input cycle host to memory transfer v cc (min) ht hl hv hv hv hv quad latency (dummy) cycle v cc (min) ht hl x x x x quad output cycle memory to host transfer v cc (min) ht hl mv mv mv mv
document number: 002-00497 rev. *e page 17 of 90 s25FL116K, s25fl132k, s25fl164k 3.3.3 interface standby when cs# is high the spi interface is in standby state. inputs are ignored. the interface waits for the beginning of a new comm and. the next interface state is instruction cycle when cs# goes low to begin a new command. while in interface standby state the memory device draws standby current (i sb ) if no embedded algorithm is in progress. if an embedded algorithm is in progress, the related current is drawn unt il the end of the algorithm when the entire device returns t o standby current draw. 3.3.4 instruction cycle when the host drives the msb of an instruction and cs# goes low, on the next rising edge of sck the device captures the msb of the instruction that begins the new command. on each following ri sing edge of sck the device captures the next lower significan ce bit of the 8-bit instruction. the host keeps cs# low, hold# high, and drives wr ite protect (wp#) signal as needed for the instruction. however, wp# is only relevant during instruction cycles of a write stat us registers command and is otherwise ignor ed. each instruction selects the addr ess space that is operated on and the transfer format used during the remainder of the command . the transfer format may be single, dual outpu t, quad output, dual i/o, or quad i/o. th e expected next interface state depends o n the instruction received. some commands are stand alone, needing no address or data transfer to or from the memory. the ho st returns cs# high after the rising edge of sck for the eighth bit of the in struction in such commands. the next inte rface state in this case is interface s tandby. 3.3.5 hold when quad mode is not enabled (sr2[1]=0) the hold# / io3 si gnal is used as the hold# input. the host keeps hold# low, sck may be at a valid level or continue toggli ng, and cs# is low. when hold# is low a command is paused, as though sck were held low. si / io0 and so / io1 ignore the input level when acting as inputs and are high impedance when acting as outputs during hold state. whether these signals are input or output depends on the command and the poi nt in the command sequence when hold# is asserted low. when hold# returns high the next state is the same state the interface was in just before hold# was asserted low. 3.3.6 single input cycle ? host to memory transfer several commands transfer information after the instruction on the single serial input (si) signal from host to the memory devi ce. the dual output, and quad output commands send address to the memory using only si but return read data using the i/o signals. the host keeps cs# low, hold# high, and drives si as needed for th e command. the memory does not drive the serial output (so) signal. the expected next interface state depends on the instruction. some instructions continue sending address or data to the memory using additional single input cycles. others may transition to single latency, or directly to single, dual, or quad output. 3.3.7 single latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determined by the instruction. during the latency cycles, the host keeps cs# low, and hold# high. the write protect (wp# ) signal is ignor ed. the host may drive the si sig nal during these cycles or the hos t may leave si floating. the memory does no t use any data driven on si / i/o0 or other i/o signals during the latency cycles. in du al or quad read commands, the host must stop driving the i/o signals on the falling edge at the end of the last latency cycle. it is recommended that the host stop driving i/o signals dur ing latency cycles so that there is su fficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. this prev ents driver conf lict between host an d memory when the signal directi on changes. the memory does not drive the serial outp ut (so) or i/o signals during the latency cycles. the next interface state depends on the comm and structure i.e. the number of latency cycles, and whether the read is single, du al, or quad width.
document number: 002-00497 rev. *e page 18 of 90 s25FL116K, s25fl132k, s25fl164k 3.3.8 single output cycle ? memory to host transfer several commands transfer inform ation back to the host on the single serial ou tput (so) signal. the host keeps cs# low, and hold# high. the write protect (wp#) signal is ignored. the memory ignores the serial input (si) signal. the memory drives so with data. the next interface state continues to be single output cycle until the host returns cs# to high ending the command. 3.3.9 dual input cycle ? ho st to memory transfer the read dual i/o command transfers two address or mode bits to the memory in each cycle. the host keeps cs# low, hold# high. the write protect (wp#) signal is ignored. the host drives address on si / io0 and so / io1. the next interface st ate following the delivery of address a nd mode bits is a dual latency c ycle if there are latency cycles ne eded or dual output cycle if no latency is required. 3.3.10 dual latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are determined by the instruction. during the latency cycles, the host keeps cs# low, and hold# high. the write protect (wp#) signal is ignored. the host may drive the si / io0 and so / io1 signals during these cycles or the host may leave si / io0 and so / io1 floating. the memory does not use any data driven on si / io0 and so / io1 duri ng the latency cycles. the host must stop driving si / io0 and so / io1 on the falling edge at the end of the last latency cycle. it is recommended that the h ost stop driving them during all latency cycles so that there is sufficient time for the host driv ers to turn off before the memory begins to drive at the end of the latency cycles. this prevents driver conf lict between host and memory when the signal direction changes . the memory does not drive the si / io0 and so / io1 signals during the latency cycles. the next interface state fo llowing the last la tency cycle is a du al output cycle. 3.3.11 dual output cycle ? memory to host transfer the read dual output and read dual i/o return data to the hos t two bits in each cycle. the host keeps cs# low, and hold# high. the write protect (wp#) signal is ignored. the memory drives data on the si / io0 and so / io1 signals during the dual output cycles. the next interface state continues to be dual output cycl e until the host returns cs# to high ending the command. 3.3.12 quad input cycle ? host to memory transfer the read quad i/o command transfers four address, mode, or data bits to the memory in each cycle. the host keeps cs# low, and drives the io signals. for read quad i/o the next interface state following the delivery of address and mode bi ts is a quad latency cycle if there are latency cycles needed or quad output cycle if no latency is required. 3.3.13 quad latency (dummy) cycle read commands may have zero to several late ncy cycles during which read data is read fr om the main flash memory array before transfer to the host. the number of latency cycles are dete rmined by the latency control in t he status registe r-3 (sr3[3:0]). d uring the latency cycles, the host keeps cs# low. the host may drive the io signals dur ing these cycles or the host may leave the io floating. the memory does not use any data driven on io during the latency cycles . the host must stop driving the io signals on the falling edge at the end of the la st latency cycle. it is recomm ended that the host st op driving them during all latency cycles so that there is sufficient time for the host drivers to turn off before the memory begins to drive at the end of the latency cycles. t his prevents driver conflict between host and memory when the signal direction changes. the memory does not drive the io signals during the latency cycles. the next interface state following the la st latency cycle is a quad output cycle.
document number: 002-00497 rev. *e page 19 of 90 s25FL116K, s25fl132k, s25fl164k 3.3.14 quad output cycle ? memory to host transfer the read quad output and r ead quad i/o return data to the ho st four bits in each cycle. the host keeps cs# lo w. the memory drives data on io0-io3 signal s during the qu ad output cycles. the next interface state continues to be quad output c ycle until the host returns cs# to high ending the command. 3.4 status register e ffects on the interface the status register-2, bit 1 (sr2[1]), selects whether quad mode is enabled to ignore hold# and wp# and allow read quad output, and read quad i/o commands. 3.5 data protection some basic protection against unintended changes to stored data are provided and controlled purel y by the hardware design. thes e are described below. other software managed protection method s are discussed in the software section of this document. 3.5.1 low power when v cc is less than v wi the memory device will ignore commands to ensure that program and erase operations can not start when the core supply voltage is out of the operating range. 3.5.2 power-up program and erase operations continue to be pr evented during the power-up to write delay (t puw ) because no write command is accepted until after t puw . 3.5.3 deep power-down (dpd) in dpd mode the device responds only to the resume from dp d command (res abh). all other commands are ignored during dpd mode, thereby protecting the memory from program and erase operations. 3.5.4 clock pulse count the device verifies that all prog ram, erase, and write st atus registers commands consist of a clock pulse count that is a multi ple of eight before executing them. a comm and not having a multiple of 8 clock pulse count is ignored and no error status is set for t he command.
document number: 002-00497 rev. *e page 20 of 90 s25FL116K, s25fl132k, s25fl164k 4. electrical characteristics 4.1 absolute maximum ratings notes: 1. this device has been designed and tested for the specified oper ation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cause permanent damage. 2. compliant with jedec standard j-std-20c for small body sn-pb or pb-free (green) assembly and the european directive on restri ctions on hazardous substances (rohs) 2002/95/eu. 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). 4.1.1 input sign al overshoot during dc conditions, input or i/o signals should remain equal to or between v ss and v cc . during voltage transitions, inputs or i/os may overshoot v ss to negative v iot or overshoot to positive v iot , for periods up to 20 ns. figure 4.1 maximum negative overshoot waveform figure 4.2 maximum positive overshoot waveform table 4.1 absolute maximum ratings parameters (1) symbol conditions range unit supply voltage v cc ?0.6 to +4.0 v voltage applied to any pin v io relative to ground ?0.6 to +4.0 v transient voltage on any pin v iot < 20 ns transient relative to ground ?2.0 to 6.0 v storage temperature t stg ?65 to +150 c lead temperature t lead (2) c electrostatic discharge voltage v esd human body model (3) ?2000 to +2000 v v il v iot < 20 ns < 20 ns < 20 ns v ih v iot < 20 ns < 20 ns < 20 ns
document number: 002-00497 rev. *e page 21 of 90 s25FL116K, s25fl132k, s25fl164k 4.1.2 latchup characteristics note: 1. excludes power supply v cc . test conditions: v cc = 3.0v, one connection at a time tested, connections not being tested are at v ss . 4.2 thermal resistance 4.3 operating ranges operating ranges define those limits between whic h functionality of the device is guaranteed. note: 1. v cc voltage during read can operate across the min and max range but should not exceed 10% of the voltage used during programmin g or erase of the data being read. table 4.2 latchup specification description min max unit input voltage with respect to v ss on all input only connections ?1.0 v cc + 1.0 v input voltage with respect to v ss on all i/o connections ?1.0 v cc + 1.0 v v cc current ?100 +100 ma table 4.3 thermal resistance parameter description soa008 soc008 fab024 fac024 wson unit theta ja thermal resistance (junction to ambient) 75 75 39 39 18 c/w table 4.4 operating ranges parameter symbol conditions spec unit min max ambient temperature t a industrial -40 +85 c industrial plus -40 +105 extended -40 +125 supply voltage v cc industrial and industrial plus temp 2.7 3.6 v extended temp 2.6 3.6
document number: 002-00497 rev. *e page 22 of 90 s25FL116K, s25fl132k, s25fl164k 4.4 dc electrical characteristics notes: 1. tested on sample basis and specified through design and characterization data. t a = 25c, v cc = 3v. 2. checker board pattern. read current is same for 125c operation. 3. 45 mhz for 125c operation. 4. for 125c operation: 2.7v: 97 mhz for 16 mb, 32 mb, and 64 mb 2.6v: 50 mhz for 16 mb, 70 mhz for 32 mb, and 97 mhz for 64 mb table 4.5 dc electrical characteristics parameter symbol conditions min typ max unit -40 to 85c -40 to 105c -40 to 125c input leakage i li 2 a i/o leakage i lo 2 a standby current i cc1 cs# = v cc , v in = gnd or v cc 15 25 25 35 a deep power-down current (s25FL116K) i cc2 cs# = v cc , v in = gnd or v cc 25 5 20a deep power-down current (s25fl132k / s25fl164k) i cc2 cs# = v cc , v in = gnd or v cc 2 8 10 20 a current: read single / dual / quad 1 mhz (2) i cc3 sck = 0.1 v cc / 0.9 v cc so = open 4 / 5 / 6 6 / 7.5 / 9 6 / 7.5 / 9 6 / 7.5 / 9 ma current: read single / dual / quad 33 mhz (2) i cc3 sck = 0.1 v cc / 0.9 v cc so = open 6 / 7 / 8 9 / 10.5 / 12 9 / 10.5 / 12 9 / 10.5 / 12 ma current: read single / dual / quad 50 mhz (2) (3) i cc3 sck = 0.1 v cc / 0.9 v cc so = open 7 / 8 / 9 10 / 12 / 13.5 10 / 12 / 13.5 10 / 12 / 13.5 ma current: read single / dual / quad 108 mhz (2) (4) i cc3 sck = 0.1 v cc / 0.9 v cc so = open 12 / 14 / 16 18 / 22 / 25 18 / 22 / 25 18 / 22 / 25 ma current: write status registers i cc4 cs# = v cc 812 12 12ma current page program i cc5 cs# = v cc 20 25 25 25 ma current sector / block erase i cc6 cs# = v cc 20 25 25 25 ma current chip erase i cc7 cs# = v cc 20 25 25 25 ma input low voltage (s25FL116K) v il -0.5 v cc x 0.2 v cc x 0.2 v cc x 0.2 v input low voltage (s25fl132k / s25fl164k) v il -0.5 v cc x 0.3 v cc x 0.3 v cc x 0.3 v input high voltage v ih v cc x 0.7 v cc + 0.4 v cc + 0.4 v cc + 0.4 v output low voltage v ol i ol = 100 a v ss 0.2 0.2 0.2 v i ol = 1.6 ma v ss 0.4 0.4 0.4 output high voltage v oh i oh = ?100 a v cc ? 0.2 v cc v cc v cc v
document number: 002-00497 rev. *e page 23 of 90 s25FL116K, s25fl132k, s25fl164k 4.4.1 active power and standby power modes the device is enabled and in the active power mode when chip se lect (cs#) is low. when cs# is high, the device is disabled, but may still be in an active power mode until all program, erase, and write operations have complete d. the device then goes into t he standby power mode, and powe r consumption drops to i sb . 4.5 ac measurement conditions figure 4.3 test setup notes: 1. output high-z is defined as the point where data is no longer driven. 2. input slew rate: 1.5 v/ns. 3. ac characteristics tables assume clock and data signals have the same slew rate (slope). figure 4.4 input, output, and timing reference levels 4.5.1 capacitance characteristics notes: 1. sampled, not 100% tested. 2. test conditions ta = 25c, f = 1.0 mhz. table 4.6 ac measurement conditions symbol parameter min max unit c l load capacitance 30 pf tr, tf input rise and fall times 2.4 ns input pulse voltage 0.2 x v cc to 0.8 v cc v input timing ref voltage 0.5 v cc v output timing ref voltage 0.5 v cc v table 4.7 capacitance parameter test conditions min max unit c in input capacitance (applies to sck, cs#) 1 mhz 8 pf c out output capacitance (applies to all i/o) 1 mhz 8 pf device under te s t c l v cc + 0.4v 0.7 x v cc 0.3 x v cc - 0.5v timing reference level 0.5 x v cc v cc 0.2v to 0.4v input levels output levels v cc - 0.2v v ss
document number: 002-00497 rev. *e page 24 of 90 s25FL116K, s25fl132k, s25fl164k 4.6 power-up timing note: 1. these parameters are characterized only. figure 4.5 power-up timing and voltage levels figure 4.6 power-down and voltage drop table 4.8 power-up timing and voltage levels parameter symbol spec unit min max v cc (min) to cs# low t vsl 10 s power-up to write ? time delay before write command t puw 10 ms write inhibit threshold voltage v wi 2.4 v power-down time t pd 10.0 s v cc power-down reset threshold voltage v cc low 1.0 v v cc v cc (max) v cc (min) v wi time reset state read instructions allowed device is fully accessible program, erase, and write instructions are ignored cs# must track v cc t puw t vsl t pd no device access allowed t vsl device read allowed vcc (max) vcc (min) time vcc vcc (low)
document number: 002-00497 rev. *e page 25 of 90 s25FL116K, s25fl132k, s25fl164k 4.7 power-on (cold) reset the device executes a power-on reset (por) process until a time delay of t puw has elapsed after the moment that v cc rises above the v wi threshold. see figure 4.5 on page 24 , figure 4.6 on page 24 , and table on page 24 . the device must not be selected (cs# to go high with v cc ) until after (t vsl ), i.e. no commands may be sent to the device until the end of t vsl . 4.8 ac electrical characteristics table 4.9 ac electrical characteristics: ?40 c to +85c/105c at 2.7v to 3.6v description symbol alt spec unit min typ max clock frequency for all spi commands except for read data command (03h) and fast read command (0bh) 2.7 v - 3.6v v cc f r f c d.c. 108 mhz clock frequency for read data command (03h) f r d.c. 50 mhz clock frequency for all fast read commands sio and mio f fr d.c. 108 mhz clock period p sck 9.25 ns clock high, low time for f fr t clh , t cll (1) t ch , t cl 3.3 ns clock high, low time for f r t clh , t cll (1) t ch , t cl 4.3 ns clock high, low time for f r t crlh , t crll (1) t ch , t cl 6 ns clock rise time t clch (2) t crt 0.1 v/ns clock fall time t chcl (2) t cft 0.1 v/ns cs# active setup time relative to sck t slch t css 5 ns cs# not active hold time relative to sck t chsl t csh 5 ns data in setup time t dvch t su 2 ns data in hold time t chdx t hd 5 ns cs# active hold time relative to sck t chsh t css 5 ns cs# not active setup time relative to sck t shch t csh 5 ns cs# deselect time (for array read -> array read) t shsl1 t cs1 7 ns cs# deselect time (for erase or program -> read status registers) t shsl2 t cs2 40 ns volatile status register write time 40 cs# deselect time (for erase or program -> suspend command) t shsl3 t cs3 130 ns output disable time t shqz (2) t dis 7 ns clock low to output valid, 30 pf, 2.7v - 3.6v t clqv1 t v1 7 ns clock low to output valid, 15 pf, 2.7v - 3.6v t clqv1 t v1 6 ns clock low to output valid (for read id commands) 2.7v - 3.6v t clqv2 t v2 8.5 ns output hold time t clqx t ho 2 ns hold# active setup time relative to sck t hlch 5 ns hold# active hold time relative to sck t chhh 5 ns
document number: 002-00497 rev. *e page 26 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and / or charac terization, not 100% tested in production. 3. only applicable as a constraint for a write status registers command when status regist er protect 0 (srp0) bit is set to 1. o r wpsel bit = 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. all program and erase times are tested using a random data pattern. 6. for 10k cycles. 85 ms at 100k cycles. hold# not active setup ti me relative to sck t hhch 5 ns hold# not active hold time relative to sck t chhl 5 ns hold# to output low-z t hhqx (2) t lz 7ns hold# to output high-z t hlqz (2) t hz 12 ns write protect setup time before cs# low t whsl (3) t wps 20 ns write protect hold time after cs# high t shwl (3) t wph 100 ns cs# high to power-down mode t dp (2) 3 s cs# high to standby mode without electronic signature read t res1 (2) 3 s cs# high to standby mode with electronic signature read t res2 (2) 1.8 s cs# high to next command after suspend t sus (2) 20 s write status registers time t w 2 30 (6) ms byte program time (first byte) (4)(5) t bp1 15 50 s additional byte program time (after first byte) (4)(5) t bp2 2.5 12 s page program time (105c / 125c) (5) t pp 0.7 3 ms sector erase time (4 kb) (5) t se 50 450 ms block erase time (64 kb) (5) t be2 500 2000 ms chip erase time 16 mb / 32 mb / 64 mb (5) t ce 11.2 / 32 / 64 64 / 128 / 256 s end of reset instruction to ce# high t rch (2) 40 ns ce# high to next instruction after reset t rst (2) 1.5 s table 4.10 ac electrical characteristics ? -40c to 125c at 2.6v/2.7v to 3.6v description symbol conditions alt spec unit min typ max s25FL116K max s25fl132k max s25fl164k clock frequency for all spi commands except for read data command (03h) and fast read command (0bh) f r 2.6v - 3.6v f c d.c. 50 70 97 mhz 2.7v - 3.6v 97 97 97 clock frequency for read data command (03h) f r 2.6v - 3.6v d.c. 45 45 45 mhz clock frequency for all fast read commands sio and mio f fr 2.6v - 3.6v d.c. 50 70 97 mhz 2.7v - 3.6v 97 97 97 table 4.9 ac electrical characteristics: ?40c to +85c/105c at 2.7v to 3.6v (continued) description symbol alt spec unit min typ max
document number: 002-00497 rev. *e page 27 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and / or characterizati on, not 100% tested in production. bytes programmed. 3. all program and erase times are tested using a random data pattern. 4. for all other ac parameters, refer to table 4.9 . 4.8.1 clock timing figure 4.7 clock timing 4.8.2 input / output timing figure 4.8 spi single bit input timing clock high, low time for f fr t clh , t cll (1) 2.6v - 3.6v t ch , t cl 4.5 ns cs# active hold time relative to sck t chsh t css 8ns hold# to output low-z t hhqx (2) t lz 999ns page program time (3) t pp 0.7 4.5 4.5 4.5 ms table 4.10 ac electrical characteristics ? -40c to 125c at 2.6v/2.7v to 3.6v description symbol conditions alt spec unit min typ max s25FL116K max s25fl132k max s25fl164k v il max v ih min t ch t crt t cft t cl v cc / 2 p sck cs# sck si so msb in lsb in t css t css t csh t csh t cs t su t hd
document number: 002-00497 rev. *e page 28 of 90 s25FL116K, s25fl132k, s25fl164k figure 4.9 spi single bit output timing figure 4.10 spi mio timing figure 4.11 hold timing cs# sck si so msb out lsb out t cs t ho t v t dis t lz cs# sck io msb in lsb in msb out lsb out t csh t csh t css t css t su t hd t lz t ho t cs t dis t v cs# sck hold# si_or_io_(during_input) so_or_io_(during_output) a b b c d e t hz t hz t lz t lz t chhl t chhl t hlch t hlch t chhh t chhh t hhch t hhch hold condition standard use hold condition non-standard use
document number: 002-00497 rev. *e page 29 of 90 s25FL116K, s25fl132k, s25fl164k figure 4.12 wp# input timing figure 4.13 software reset input timing cs# wp# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 write status registers instruction input data t wps t wph cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 software reset enable inst. (66h) software reset instruction (99h) reset to next instr. t cs2 t rch t rst
document number: 002-00497 rev. *e page 30 of 90 s25FL116K, s25fl132k, s25fl164k 5. physical interface 5.1 connection diagrams 5.1.1 soic 8 figure 5.1 8-pin plastic small outline package (so) 5.1.2 soic 16 ? s25fl164k figure 5.2 16-pin plastic small outline package (so) 5.1.3 wson 8 figure 5.3 8-contact wson (5 mm x 6 mm) package / 8-contact uson (4 mm x 4 mm) package 1 2 3 4 cs# so/io1 wp#/io2 v ss si/io0 sck hold#/io3 v cc 5 6 7 8 1 2 3 4 16 15 14 13 hold#/io3 v cc dnu dnu dnu dnu si/io0 sck 5 6 7 8 12 11 10 9 wp#/io2 v ss dnu dnu dnu dnu cs# so/io1 1 2 3 4 5 6 7 8 cs# so/io1 hold#/io3 sck si/io0 v ss wson wp#/io2 v cc
document number: 002-00497 rev. *e page 31 of 90 s25FL116K, s25fl132k, s25fl164k 5.1.4 fab024 24-ball bga figure 5.4 24-ball bga package, 5x5 ball configuration, top view 5.1.5 fac024 24-ba ll bga package figure 5.5 24-ball bga package, 6x4 ball configuration, top view note: 1. signal connections are in the same relati ve positions as fab024 bga, allowing a si ngle pcb footprint to use either package. 5.1.6 special handl ing instructions for fbga packages flash memory devices in bga packages may be damaged if exposed to ultrasonic cleaning methods. the package and / or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. 3 24 1 nc nc rfu b d e a c v ss sck v cc dnu rfu cs# wp#/io2 dnu si/io0 so/io1 hold#/io3 dnu nc nc rfu nc nc nc nc nc nc 5 3 24 1 nc nc rfu b d e a c v ss sck v cc dnu rfu cs# wp#/io2 dnu si/io0 so/io1 hold#/io3 dnu nc nc rfu nc nc nc nc nc nc f
document number: 002-00497 rev. *e page 32 of 90 s25FL116K, s25fl132k, s25fl164k 5.2 physical diagrams 5.2.1 soa008 ? 8-lead plast ic small outline packag e (150-mils body width) g1019 \ 16-038.3f \ 10.06.11 notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane.
document number: 002-00497 rev. *e page 33 of 90 s25FL116K, s25fl132k, s25fl164k 5.2.2 soc008 ? 8-lead plast ic small outline packag e (208-mils body width) 3602 \ 16-038.03 \ 9.1.6 notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane. package soc 008 (inches) soc 008 (mm) jedec symbol min max min max a 0.069 0.085 1.753 2.159 a1 0.002 0.0098 0.051 0.249 a2 0.067 0.075 1.70 1.91 b 0.014 0.019 0.356 0.483 b1 0.013 0.018 0.330 0.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.008 0.152 0.203 d 0.208 bsc 5.283 bsc e 0.315 bsc 8.001 bsc e1 0.208 bsc 5.283 bsc e .050 bsc 1.27 bsc l 0.020 0.030 0.508 0.762 l1 .049 ref 1.25 ref l2 .010 bsc 0.25 bsc n 8 8 0? 8? 0? 8? 1 5? 15? 5? 15? 2 0? 0?
document number: 002-00497 rev. *e page 34 of 90 s25FL116K, s25fl132k, s25fl164k 5.2.3 so3016 ? 16-lead plast ic wide outline package (300-mils body width) (s25fl164k)
document number: 002-00497 rev. *e page 35 of 90 s25FL116K, s25fl132k, s25fl164k 5.2.4 wnd008 ? 8-cont act wson 5 mm ? 6 mm symbol min nom max notes e 1.27 bsc. n 8 3 nd 4 5 l 0.55 0.60 0.65 b 0.35 0.40 0.45 4 d2 3.90 4.00 4.10 e2 3.30 3.40 3.50 d 5.00 bsc e 6.00 bsc a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref k 0.20 min. package wnd008 g5026 \ 16-038.30 \ 03.20.14 notes: 1. dimensioning and tolerancing conforms to asme y14.5m-1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should not be measured in that radius area. 5 nd refers to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burr is 0.076mm in all directions. 8 pin #1 id on top will be located within the indicated zone. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals.
document number: 002-00497 rev. *e page 36 of 90 s25FL116K, s25fl132k, s25fl164k 5.2.5 unf008 ? 8-cont act uson 4 mm x 4 mm symbol min nom max note e 0.80 bsc. n 8 3 nd 4 5 l 0.35 0.40 0.45 b 0.25 0.30 0.35 4 d2 2.20 2.30 2.40 e2 2.90 3.00 3.10 d 4.00 bsc e 4.00 bsc a 0.50 0.55 0.60 a1 0.00 0.035 0.05 a3 0.152 ref k 0.20 min. g5052 \ 16-038.30 \ 09.17.15 notes: 1. dimensioning and tolerancing conforms to asme y14.5m - 1994. 2. all dimensions are in millmeters. 3. n is the total number of terminals. 4 dimension ?b? applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension ?b? should not be measured in that radius area. 5 nd refers to the number of terminals on d side. 6. max. package warpage is 0.05mm. 7. maximum allowable burr is 0.076mm in all directions. 8 pin #1 id on top will be located within the indicated zone. 9 bilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. package unf008
document number: 002-00497 rev. *e page 37 of 90 s25FL116K, s25fl132k, s25fl164k 5.2.6 fab024 ? 24-ball ba ll grid array (8 mm ? 6 mm) package
document number: 002-00497 rev. *e page 38 of 90 s25FL116K, s25fl132k, s25fl164k 5.2.7 fac024 ? 24-ball ba ll grid array (8 mm ? 6 mm) package package fac024 jedec n/a d x e 8.00 mm x 6.00 mm nom package symbol min nom max note a --- --- 1.20 profile a1 0.25 --- --- ball height a2 0.70 --- 0.90 body thickness d 8.00 bsc. body size e 6.00 bsc. body size d1 5.00 bsc. matrix footprint e1 3.00 bsc. matrix footprint md 6 matrix size d direction me 4 matrix size e direction n 24 ball count ? b 0.35 0.40 0.45 ball diameter e 1.00 bsc. ball pitchl sd/ se 0.5/0.5 solder ball placement depopulated solder balls j package outline type 3642 f16-038.9 \ 09.10.09 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 outline and dimensions per customer requirement.
document number: 002-00497 rev. *e page 39 of 90 s25FL116K, s25fl132k, s25fl164k software interface this section discusses the features and behaviors most relevant to host system software that interacts with s25fl1-k memory devices. 6. address space maps 6.1 overview many commands operate on the main flash memory array. some commands operate on address spaces separate from the main flash array. each separate address space uses the full 24-bit address but may only define a smal l portion of the available addr ess space. 6.2 flash memory array the main flash array is divided into erase units calle d sectors. the sectors are uniform 4 kbytes in size. note : these are condensed tables that use a coup le of sectors as references. there are add ress ranges that are not explicitly liste d. all 4-kb sectors have the pattern xxx000h-xxxfffh. table 6.1 s25FL116K main memory address map sector size (kbyte) sector count sector range address range (byte address) notes 4 512 sa0 000000h-000fffh sector starting address ? sector ending address : : sa511 1ff000h-1fffffh table 6.2 s25fl132k main memory address map sector size (kbyte) sector count sector range address range (byte address) notes 4 1024 sa0 000000h-000fffh sector starting address ? sector ending address : : sa1023 3ff000h-3fffffh table 6.3 s25fl164k main memory address map sector size (kbyte) sector count sector range address range (byte address) notes 4 2048 sa0 000000h-000fffh sector starting address ? sector ending address : : sa2047 7ff000h-7fffffh
document number: 002-00497 rev. *e page 40 of 90 s25FL116K, s25fl132k, s25fl164k 6.3 security registers the s25fl1-k provides four 256-byte security registers. each r egister can be used to store info rmation that can be permanently protected by programming one time programmable (otp) lock bits in status register-2. register 0 is used by cypress to store and protect the serial flash discoverable parameters (sfdp) information that is also accessed by the read sfdp command. see section 6.4 . the three additional security registers can be erased, programm ed, and protected individually. these registers may be used by system manufacturers to store and permanently protect security or other important information se parate from the main memory array. 6.4 security register 0 ? serial flash discoverable parameters (sfdp ? jedec jesd216b) this document defines the serial flash discoverable paramete rs (sfdp) revision b data st ructure for s25fl1-k family. these data structure values are an update to the earlier revision sfdp data st ructure in the s25fl1-k family devices. the read sfdp (rsfdp) command (5ah) reads information from a separate flash memory address space for device identification, feature, and configuration information, in accord with the je dec jesd216b standard for serial flash discoverable parameters. the sfdp data structure consists of a header table that identifies the revision of th e jesd216 header format that is supported and provides a revision number and pointer for each of the sfdp param eter tables that ar e provided. the parameter tables follow the sfdp header. however, the parameter tables may be placed in any physical location and order within the sfdp address space. the tables are not necessarily adjacent nor in the same order as their header table entries. the sfdp header points to the following parameter tables: ? basic flash ? this is the original sfdp table. it has a few modified fields and new additional field added at the end of the table. ? sector map ? this is the original sfdp table. it has a few modified fields and new additional field added at the end of the table. the physical order of the tables in the sfdp address space is : sfdp header, cypress vendor spec ific, basic flash, and sector map. the sfdp address space is programmed by cypress and read-only for the host system. table 6.4 security register addresses security register address 0 (sfdp) 000000h - 0000ff 1 001000h - 0010ff 2 002000h - 0020ff 3 003000h - 0030ff
document number: 002-00497 rev. *e page 41 of 90 s25FL116K, s25fl132k, s25fl164k 6.4.1 serial flash discoverable parameters (sfdp) address map the sfdp address space has a header starting at address zero that identifies the sfdp data stru cture and provides a pointer to each parameter. one basic flash parameter is mandated by the jedec jesd216b standard. 6.4.2 sfdp header field definitions table 6.5 sfdp overview map ? security register 0 byte address description 0000h location zero within jedec jesd216b sfdp space ? start of sfdp header ,,, remainder of sfdp header followed by undefined space 0080h start of sfdp parameter ... remainder of sfdp jedec parameter followed by undefined space 00bfh end of sfdp space 00c0h to 00f7h reserved space 00f8h to 00ffh unique id table 6.6 sfdp header sfdp byte address sfdp dword name data description 00h sfdp header 1st dword 53h this is the entry point for read sfdp (5 ah) command i.e. location zero within sfdp space ascii ?s? 01h 46h ascii ?f? 02h 44h ascii ?d? 03h 50h ascii ?p? 04h sfdp header 2nd dword 06h sfdp minor revision (06h = jedec jesd216 revision b) ? this revision is backward compatible with all prior minor revisions. minor revisions are changes that define previously reserved fields, add fields to the end, or that clarify definitions of existing fi elds. increments of the minor revision value indicate that previously reserved parameter fields may have been assigned a new definition or entire dwords may have been added to the parameter table. however, the definition of previously existing fields is unchanged and therefore remain backward compatible with earlier sfdp parameter table revisions. software can safely ignore increments of the minor revision number, as long as only those parameters the software was designed to support are used i.e. previously reserved fields and additional dwords must be masked or ignored. do not do a simple compare on the minor revision number, looking only for a match with the revision number that the softwa re is designed to handle. there is no problem with using a higher number minor revision. 05h 01h sfdp major revision ? this is the original major revision. this major revision is compatible with all sfdp reading and parsing software. 06h 03h number of parameter headers (zero based, 03h = 4 parameters) 07h ffh unused
document number: 002-00497 rev. *e page 42 of 90 s25FL116K, s25fl132k, s25fl164k 08h parameter header 0 1st dword 00h parameter id lsb (00h = jedec sfdp basic spi flash parameter) 09h 00h parameter minor revision (00h = jesd216) ? this older revision parameter header is provided for any legacy sfdp reading and parsing software that requires seeing a minor revision 0 parameter header. sfdp software designed to handle later minor revisions should continue reading parameter headers looking for a higher numbered minor revision that contains additional parameters for that software revision. 0ah 01h parameter major revision (01h = the original major revision - all sfdp software is compatible with this major revision. 0bh 09h parameter table length (in double words = dwords = 4-byte units) 09h = 9 dwords 0ch parameter header 0 2nd dword 80h parameter table pointer byte 0 (dword = 4-byte aligned) jedec basic spi flash parameter byte offset = 80h 0dh 00h parameter table pointer byte 1 0eh 00h parameter table pointer byte 2 0fh ffh parameter id msb (ffh = je dec defined legacy parameter id) 10h parameter header 1 1st dword efh parameter id lsb (efh = winbond legacy spi flash parameter) 11h 00h parameter minor revision (00h = jesd216) ? this older revision parameter header is provided for any legacy sfdp reading and parsing software that requires seeing a minor revision 0 parameter header. sfdp software designed to handle later minor revisions should continue reading parameter headers looking for a later minor revision that contains additional parameters. 12h 01h parameter major revision (01h = the original major revision ? all sfdp software is compatible with this major revision. 13h 04h parameter table length (in double words = dwords = 4-byte units) 04h = 4 dwords 14h parameter header 1 2nd dword 80h parameter table pointer byte 0 (dword = 4-byte aligned) jedec basic spi flash parameter byte offset = 0080h address 15h 00h parameter table pointer byte 1 16h 00h parameter table pointer byte 2 17h ffh parameter id msb (ffh = jedec defined parameter) 18h parameter header 2 1st dword 00h parameter id lsb (00h = jedec sfdp basic spi flash parameter) 19h 06h parameter minor revision (06h = jesd216 revision b) 1ah 01h parameter major revision (01h = the original major revision - all sfdp software is compatible with this major revision. 1bh 10h parameter table length (in double words = dwords = 4-byte units) 10h = 16 dwords 1ch parameter header 2 2nd dword 80h parameter table pointer byte 0 (dword = 4-byte aligned) jedec basic spi flash parameter byte offset = 0080h address 1dh 00h parameter table pointer byte 1 1eh 00h parameter table pointer byte 2 1fh ffh parameter id msb (ffh = jedec defined parameter) table 6.6 sfdp header (continued) sfdp byte address sfdp dword name data description
document number: 002-00497 rev. *e page 43 of 90 s25FL116K, s25fl132k, s25fl164k 6.4.3 jedec sfdp basi c spi flash parameter 20h parameter header 3 1st dword 01h parameter id lsb (spansion v endor specific id parameter) legacy manufacturer id 01h = amd / spansion 21h 01h parameter minor revision (01h = id updated with sfdp rev b table) 22h 01h parameter major revision (01h = the original major revision - all sfdp software that recognizes this parameter?s id is compatible with this major revision. 23h 00h parameter table length (in double words = dwords = 4-byte units) 00h not implemented 24h parameter header 3 2nd dword 00h parameter table pointer byte 0 (dword = 4-byte aligned) 25h 00h parameter table pointer byte 1 26h 00h parameter table pointer byte 2 27h 01h parameter id msb (01h = jedec jep106 bank number 1) table 6.7 basic spi flash parameter, jedec sfdp rev b sfdp parameter relative byte address sfdp dword name data description 00h jedec basic flash parameter dword-1 e5h start of sfdp jedec parameter bits 7:5 = unused = 111b bit 4:3 = 05h is volatile status r egister write instruction and status register is default non-volatile= 00b bit 2 = program buffer > 64 bytes = 1 bits 1:0 = uniform 4-kb erase is s upported through out the device = 01b 01h 20h bits 15:8 = uniform 4-kb erase instruction = 20h 02h f1h bit 23 = unused = 1b bit 22 = supports qor read (1-1-4), yes = 1b bit 21 = supports qio read (1-4-4),yes =1b bit 20 = supports dio read (1-2-2), yes = 1b bit19 = supports ddr, no= 0 b bit 18:17 = number of address bytes 3 only = 00b bit 16 = supports sio and dio yes = 1b binary field: 1-1-1-1-0-00-1 nibble format: 1111_0001 hex format: f1 03h ffh bits 31:24 = unused = ffh 04h jedec basic flash parameter dword-2 ffh density in bits, zero based, 16 mb = 00ffffffh 32 mb = 01ffffffh 64 mb = 03ffffffh 05h ffh 06h ffh 07h 00h 16mb 01h 32mb 03h 64mb table 6.6 sfdp header (continued) sfdp byte address sfdp dword name data description
document number: 002-00497 rev. *e page 44 of 90 s25FL116K, s25fl132k, s25fl164k 08h jedec basic flash parameter dword-3 44h bits 7:5 = number of qi o (1-4-4)mode cycles = 010b bits 4:0 = number of fast read qio dummy cycles = 00100b for default latency code 09h ebh fast read qio (1-4-4)instruction code 0ah 08h bits 23:21 = number of quad out (1-1-4) mode cycles = 000b bits 20:16 = number of quad out dummy cycles = 01000b for default latency code 0bh 6bh quad out (1-1-4)instruction code 0ch jedec basic flash parameter dword-4 08h bits 7:5 = number of dual out (1-1-2)mode cycles = 000b bits 4:0 = number of dual out dummy cycles = 01000b for default latency code 0dh 3bh dual out (1-1 -2) instruction code 0eh 80h bits 23:21 = number of du al i/o mode cycles = 100b bits 20:16 = number of dual i/o dummy cycles = 0 0000b for default latency code 0fh bbh dual i/o instruction code 10h jedec basic flash parameter dword-5 eeh bits 7:5 rfu = 111b bit 4 = qpi (4-4-4) fast read commands not supported = 0b bits 3:1 rfu = 111b bit 0 = dual all not supported = 0b 11h ffh bits 15:8 = rfu = ffh 12h ffh bits 23:16 = rfu = ffh 13h ffh bits 31:24 = rfu = ffh 14h jedec basic flash parameter dword-6 ffh bits 7:0 = rfu = ffh 15h ffh bits 15:8 = rfu = ffh 16h ffh bits 23:21 = number of dual all mode cycles = 111b bits 20:16 = number of dual all dummy cycles = 11111b 17h ffh dual all instruction code 18h jedec basic flash parameter dword-7 ffh bits 7:0 = rfu = ffh 19h ffh bits 15:8 = rfu = ffh 1ah ffh bits 23:21 = number of qpi mo de cycles = 111b not supported bits 20:16 = number of qpi dummy cycles = 11111b for default latency code 1bh ffh qpi instruction code ?not supported ff? 1ch jedec basic flash parameter dword-8 0ch sector type 1 size 2 n bytes = 4 kb = 0ch (for uniform 4 kb) 1dh 20h sector type 1 instruction 1eh 10h sector type 2 size 2 n bytes = 64 kb = 0fh (for uniform 64 kb) 1fh d8h sector type 2 instruction 20h jedec basic flash parameter dword-9 00h sector type 3 size 2 n bytes = not supported = 00h 21h ffh sector type 3 instruction = not supported = ffh 22h 00h sector type 4 size 2 n bytes = not supported = 00h 23h ffh sector type 4 instruction = not supported = ffh table 6.7 basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description
document number: 002-00497 rev. *e page 45 of 90 s25FL116K, s25fl132k, s25fl164k 24h jedec basic flash parameter dword-10 42h bits 31:30 = sector type 4 erase, ty pical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = rfu = 11b bits 29:25 = sector type 4 erase, typical time count = rfu = 11111b (typ erase time = (count +1) * units) = rfu =11111 bits 24:23 = sector type 3 erase, ty pical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = rfu = 11b bits 22:18 = sector type 3 erase, typical time count = 00100b (typ erase time = (count +1) * units) = rfu =11111 bits 17:16 = sector type 2 erase, ty pical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 16 ms = 01b bits 15:11 = sector type 2 erase, typical time count = 11110b (typ erase time = (count +1) * units) = 31*16 ms = 496 ms bits 10:9 = sector type 1 erase, typical time units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1 s) = 16ms = 01b bits 8:4 = sector type 1 erase, typical time count = 00100b (typ erase time = (count +1) * units) = 5*16 ms = 80 ms bits 3:0 = count = (max erase time / (2 * typical erase time))- 1 = 0010b multiplier from typical erase time to maximum erase time = 6x multiplier max erase time = 2*(count +1)*typ erase time binary fields: 11-11111-11-11111-01-11110-01- 00100-0010 nibble format: 1111_1111_1111_1101_ 1111 _0010_0100_0010 hex format: ff_fd_f2_42 25h f2h 26h fdh 27h ffh table 6.7 basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description
document number: 002-00497 rev. *e page 46 of 90 s25FL116K, s25fl132k, s25fl164k 28h jedec basic flash parameter dword-11 81h bits 23 = byte program typical time, additional byte units (0b:1 s, 1b:8 s) = 1 s = 0b bits 22:19 = byte program typical time, additional byte count, (count+1)*units, count = 0010b, (typ pr ogram time = (count +1) * units) = 3*1 s =3 s bits 18 = byte program typical time, first byte units (0b:1 s, 1b:8 s) = 8 s = 1b bits 17:14 = byte program typical time, first byte count, (count+1)*units, count = 0001b, (typ program time = (count +1) * units) = 2*8 s = 16 s bits 13 = page program typical time units (0b:8 s, 1b:64 s) = 64 s = 1b bits 12:8 = page program typical ti me count, (count+1)*units, count = 01010b, (typ program time = (count +1) * units) = 11*64 s = 704 s bits 7:4 = n = 1000b, page size= 2 n = 256b page bits 3:0 = count = 0001b = (max page program time / (2 * typ page program time))- 1 multiplier from typical page prog ram time to maximum page program time = 4x multiplier max page program time = 2*(count +1)*typ page program time binary fields: 0-0010-1-0001-1-01010-1000-0001 nibble format: 0001_0100_0110_1010_1000_0001 hex format: 14_6a_81 29h 6ah 2ah 14h 2bh c2h 16mb c7h 32mb cfh 64mb 16 mb = 1100_0010b = c2h bit 31 reserved = 1b bits 30:29 = chip erase, typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 4s = 10b bits 28:24 = chip erase, typical time count, (count+1)*units, count = 00010b, (typ program time = (count +1) * units) = 3*4s = 12s 32 mb = 1100_0111b = c7h bit 31 reserved = 1b bits 30:29 = chip erase, typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 4s = 10b bits 28:24 = chip erase, typical time count, (count+1)*units, count = 00111b, (typ program time = (count +1) * units) = 8*4s = 32s 64 mb = 1100_1111b = cfh bit 31 reserved = 1b bits 30:29 = chip erase, typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b: 64 s) = 4s = 10b bits 28:24 = chip erase, typical time count, (count+1)*units, count = 01111b, (typ program time = (count +1) * units) = 16*4s = 64s table 6.7 basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description
document number: 002-00497 rev. *e page 47 of 90 s25FL116K, s25fl132k, s25fl164k 2ch jedec basic flash parameter dword-12 cch bit 31 = suspend and resume supported = 0b bits 30:29 = suspend in-progress erase max latency units (00b: 128ns, 01b: 1us, 10b: 8 s, 11b: 64 s) = 1 s= 01b bits 28:24 = suspend in-progress erase max latency count = 10011b, max erase suspend latency = (count +1) * units = 20*1 s = 20 s bits 23:20 = erase resume to suspen d interval count = 0001b, interval = (count +1) * 64 s = 2 * 64 s = 128 s bits 19:18 = suspend in-progress program max latency units (00b: 128ns, 01b: 1us, 10b: 8 s, 11b: 64 s) = 1 s= 01b bits 17:13 = suspend in-progress program max latency count = 10011b, max erase suspend latency = (count +1) * units = 20*1 s = 20 s bits 12:9 = program resume to suspend interval count = 0001b, interval = (count +1) * 64 s = 2 * 64 s = 128 s bit 8 = rfu = 1b bits 7:4 = prohibited operations during erase suspend = xxx0b: may not initiate a new erase anywhere (erase nesting not permitted) + xx0xb: may not initiate a page program anywhere + x1xxb: may not initiate a read in the erase suspended sector size + 1xxxb: the erase and program restri ctions in bits 5:4 are sufficient = 1100b bits 3:0 = prohibited operations during program suspend = xxx0b: may not initiate a new erase anywhere (erase nesting not permitted) + xx0xb: may not initiate a new page program anywhere (program nesting not permitted) + x1xxb: may not initiate a read in the program suspended page size + 1xxxb: the erase and program restri ctions in bits 1:0 are sufficient = 1100b binary fields: 0-01-10011-0001-01-10011-0001-1-1100-1100 nibble format: 0011_0011_0001_0110_0110_0011_1100_1100 hex format: 33_16_63_cc 2dh 63h 2eh 16h 2fh 33h 30h jedec basic flash parameter dword-13 7ah bits 31:24 = erase suspend instruction = 75h bits 23:16 = erase resume instruction = 7ah bits 15:8 = program suspend instruction = 75h bits 7:0 = program resu me instruction = 7ah 31h 75h 32h 7ah 33h 75h table 6.7 basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description
document number: 002-00497 rev. *e page 48 of 90 s25FL116K, s25fl132k, s25fl164k 34h jedec basic flash parameter dword-14 f7h bit 31 = deep power-down supported = 0 bits 30:23 = enter deep power-down instruction = b9h bits 22:15 = exit deep power-down instruction = abh bits 14:13 = exit deep power-down to next operation delay units = (00b: 128 ns, 01b: 1 s, 10b: 8 s, 11b: 64 s) = 1 s = 01b bits 12:8 = exit deep power-down to next operation delay count = 00010b, exit deep power-down to next operation delay = (count+1)*units = 3*1 s=3 s bits 7:4 = rfu = 1111b bit 3:2 = status register polling device busy = 01b: legacy status polling supported = use legacy polling by reading the status register with 05h instruction and checking wip bit[0] (0=ready; 1=busy). bits 1:0 = rfu = 11b binary fields: 0-10111001-10101011-01-00010-1111-01-11 nibble format: 0101_1100_1101_0101_1010_0010_1111_0111 hex format: 5c_d5_a2_f7 35h a2h 36h d5h 37h 5ch 38h jedec basic flash parameter dword-15 00h bits 31:24 = rfu = ffh bit 23 = hold and wp disable = not supported = 0b bits 22:20 = quad enable requirements = 101b: qe is bit 1 of the status regist er 2. status register 1 is read using read status instruction 05h. status register 2 is read using instruction 35h. qe is set via write status inst ruction 01h with two data bytes where bit 1 of the second byte is one. it is cleared via write status with two data bytes where bit 1 of the second byte is zero. bits 19:16 0-4-4 mode entry method = xxx1b: mode bits[7:0] = a5h note: qe must be set prior to using this mode + x0xxb: mode bits[7:0] = axh + 1xxxb: rfu = 1001b bits 15:10 0-4-4 mode exit method = xx_xxx1b: mode bits[7:0] = 00h will terminate this mode at the end of the current read operation + xx_1xxxb: input fh (mode bit reset) on dq0-dq3 for 8 clocks. this will terminate the mode prior to the next read operation. + 11_x1xx: rfu = 111101 bit 9 = 0-4-4 mode supported = 1 bits 8:4 = 4-4-4 mode enable sequences = 0_0000b: not supported bits 3:0 = 4-4-4 mode disable sequences = 0000b: not supported binary fields: 11111111-0-101-1001-111101-1-00000-0000 nibble format: 1111_1111_0101_1001_1111_0110_0000_0000 hex format: ff_59_f6_00 39h f6h 3ah 59h 3bh ffh table 6.7 basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description
document number: 002-00497 rev. *e page 49 of 90 s25FL116K, s25fl132k, s25fl164k 3ch jedec basic flash parameter dword-16 e8h bits 31:24 = enter 4-byte addressing = xxxx_xxx1b:issue instruction b7 (preceding write enable not required + xx1x_xxxxb: supports dedicated 4-byte address instruction set. consult vendor data sheet for the instruction set definition or look for 4- byte address parameter table. + 1xxx_xxxxb: reserved = 10000000b not supported bits 23:14 = exit 4-byte addressing = xx_xxxx_xxx1b:issue instruction e9h to exit 4-byte address mode (write enable instruction 06h is not required) + xx_xx1x_xxxxb: hardware reset + xx_x1xx_xxxxb: software reset (see bits 13:8 in this dword) + xx_1xxx_xxxxb: power cycle + x1_xxxx_xxxxb: reserved + 1x_xxxx_xxxxb: reserved = 11_0000_0000b not supported bits 13:8 = soft reset and rescue sequence support = x1_xxxxb: issue reset enable inst ruction 66h, then issue reset instruction 99h. the reset enable, reset sequence may be issued on 1,2, or 4 wires depending on the device operating mode = 01_0000b bit 7 = rfu = 1 bits 6:0 = volatile or non-volatile register and write enable instruction for status register 1 = xxx_1xxxb: non-volatile/v olatile status register 1 powers-up to last written value in the non-volatile stat us register, use instruction 06h to enable write to non-volatile status regi ster. volatile status register may be activated after power-up to overri de the non-volatile status register, use instruction 50h to enable write and activate the volatile status register. + x1x_xxxxb: reserved + 1xx_xxxxb: reserved = 1101000b binary fields: 10000000-1100000000-010000-1-1101000 nibble format: 1000_0000_1100_0000_0001_0000_1110_1000 hex format: 80_c0_10_e8 3dh 10h 3eh c0h 3fh 80h table 6.7 basic spi flash parameter, jedec sfdp rev b (continued) sfdp parameter relative byte address sfdp dword name data description
document number: 002-00497 rev. *e page 50 of 90 s25FL116K, s25fl132k, s25fl164k 6.5 status registers status register-1 (sr1) and status register-2 (sr2) can be used to provide status on the availability of the flash memory array , if the device is write enabled or disabled, t he state of write protection, quad spi sett ing, security register lock status, and er ase / program suspend status. sr1 and sr2 contain non-volatile bits in locations sr1[7:2] and sr2[6:0] that control sector protection, otp register protectio n, status register protection, and quad mode. bit locations sr2[7], sr1[1], and sr1[0] are read only volatile bits for suspend, wr ite enable, and busy status; t hese are updated by the memory control logic. the sr1[1] write enable bit is set only by the write en able (06h) command and cleared by the memory contro l logic when an embedded operation is completed. write access to the non-volatile status regi ster bits is controlled by the state of the non-volatile status register protect bi ts sr1[7] and sr2[0] (srp0, srp1), the write enab le command (06h) preceding a write status registers command, and while quad mode is not enabled, the wp# pin. a volatile version of bits sr2[6], sr2[1], and sr1[7:2] that c ontrol sector protection and quad mode are used to control the be havior of these features after power up. during power up or software re set, these volatile bits are l oaded from the non-volatile versi on of the status register bits. the write enable for volatile status register (50h) co mmand can be used to write these volatile bits when the command is followed by a write status registers (01h) command. this gives more flexibility to change the system configuration a nd memory protection schemes quickly without wa iting for the typical non-vo latile bit write cycles or affecting the endurance of t he status register non-volatile bits. write access to the volatile sr1 and sr2 status register bits is controlled by the state of the non-volatile status register pr otect bits sr1[7] and sr2[0] (srp0, srp1), the write enable for volatile status register command (50h) preceding a write status registers command, and while quad mode is not enabled, the wp# pin. status register-3 (sr3) is used to configur e and provide status on the variable read latency, and quad io wrapped read features . write access to the volatile sr3 status register bits is contro lled by write enable for volatile status register command (50h) preceding a write status register comm and. the srp bits do not protect sr3. table 6.8 status register-1 (sr1) bits field name function type default state description 7srp0 status register protect 0 non-volatile and volatile versions 0 0 = wp# input has no effect or power supply lock down mode 1 = wp# input can protect t he status register or otp lock down see table 6.17 on page 57 . 6 sec sector / block protect 0 0 = bp2-bp0 protect 64-kb blocks 1 = bp2-bp0 protect 4-kb sectors see table 6.13 on page 54 and table 6.14 on page 55 for protection ranges. 5tb to p / b o t t o m protect 0 0 = bp2-bp0 protect from the top down 1 = bp2-bp0 protect from the bottom up see table 6.13 on page 54 and table 6.14 on page 55 for protection ranges. 4bp2 block protect bits 0 000b = no protection see table 6.13 on page 54 and table 6.14 on page 55 for protection ranges. 3bp1 0 2bp0 0 1wel write enable latch volatile, read only 0 0 = not write enabled, no embedded operation can start 1 = write enabled, embedded operation can start 0busy embedded operation status volatile, read only 0 0 = not busy, no embedded operation in progress 1 = busy, embedded operation in progress
document number: 002-00497 rev. *e page 51 of 90 s25FL116K, s25fl132k, s25fl164k note: 1. lb0 value should be considered don't care for read. this bit is set to 1. table 6.9 status register-2 (sr2) bits field name function type default state description 7sus suspend status volatile, read only 0 0 = erase / program not suspended 1 = erase / program suspended 6cmp complement protect non-volatile and volatile versions 0 0 = normal protection map 1 = inverted protection map see table 6.13 on page 54 and table 6.14 on page 55 for protection ranges. 5lb3 security register lock bits otp 0 otp lock bits 3:0 for security registers 3:0 0 = security register not protected 1 = security register protected security register 0 contains the serial flash discoverable parameters and is always programmed and locked by spansion. 4lb2 0 3lb1 0 2lb0 1 1 qe quad enable non-volatile and volatile versions 0 (for all model numbers except ?q1?) 0 = quad mode not enabled, the wp# pin and hold# are enabled 1 = quad mode enabled, the io2 and io3 pins are enabled, and wp# and hold# functions are disabled 1 (for model number ?q1?) 1 = quad mode enabled and can not be changed, the io2 and io3 pins are enabled, and wp# and hold# functions are disabled 0srp1 status register protect 1 0 0 = srp1 selects whether wp# input has effect on protection of the status register 1 = srp1 selects power s upply lock down or otp lock down mode see table 6.17 on page 57 . table 6.10 status register-3 (sr3) bits field name function type default state description 7 rfu reserved 0 reserved for future use 6w6 burst wrap length volatile 1 00 = 8-byte wrap. data read starts at the initial address and wraps within an aligned 8-byte boundary. 01 = 16-byte wrap. data read starts at the initial address and wraps within an aligned 16-byte boundary. 10 = 32-byte wrap. data read starts at the initial address and wraps within an aligned 32-byte boundary. 11 = 64-byte wrap. data read starts at the initial address and wraps within an aligned 64-byte boundary. 5w5 1 4w4 burst wrap enable 1 0 = wrap enabled 1 = wrap disabled 3 latency control (lc) variable read latency control 0 defines the number of read latency cycles in fast read, dual out, quad out, dual io, and quad io commands. binary values for 1 to 15 late ncy cycles. a value of zero disables the variable latency mode. 20 10 00
document number: 002-00497 rev. *e page 52 of 90 s25FL116K, s25fl132k, s25fl164k 6.5.1 busy busy is a read only bit in the status regist er (sr1[0]) that is set to a 1 state when the device is executing a page program, s ector erase, block erase, chip erase, write status registers or eras e / program security register co mmand. during this time the devic e will ignore further commands except for the software reset, read status register and erase / program suspend commands (see t w , t pp , t se , t be , and t ce in section 4.8, ac electrical characteristics on page 25 ). when the program, erase or write status / security register command has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further commands. 6.5.2 write enable latch (wel) write enable latch (wel) is a read only bit in the status register (sr1[1]) that is set to 1 af ter executing a write enable com mand. the wel status bit is cleared to 0 when the device is write di sabled. a write disable state occu rs upon power-up or after any o f the following commands: write disable, page program, sector erase, bl ock erase, chip erase, write st atus registers, erase security register and program security register. the wel status bit is clea red to 0 even when a program or erase operation is prevented by the block protection bits. the wel status bit is also cleared to 0 when a progra m or erase operation is suspended. the wel stat us bit is set to 1 when a program or erase operation is resumed. 6.5.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0) are non -volatile read / write bits in the status register (sr1[4:2]) that provide write protection control and status. block protect bits can be set using the writ e status registers command (see t w in section 4.8, ac electrical characteristics on page 25 ). all, none or a portion of the memory a rray can be protected from program and erase commands (see section 6.5.7, block protection maps on page 53 ). the factory default setting for the block protection bits is 0 (none of the array is protected.) 6.5.4 top / bottom block protect (tb) the non-volatile top / bottom bit (tb sr1[5]) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in section 6.5.7, block protection maps on page 53 . the factory default setting is tb=0. the tb bit can be set with the write stat us registers command depending on the st ate of the srp0, srp1 and wel bits. 6.5.5 sector / blo ck protect (sec) the non-volatile sector / block protect bit (sec sr1[6]) controls if the block protect bits (bp2, bp1, bp0) protect either 4-kb sectors (sec=1) or 64-kb blocks (sec=0) in the top (tb= 0) or the bottom (tb=1) of the array as shown in section 6.5.7, block protection maps on page 53 . the default setting is sec=0. 6.5.6 complement protect (cmp) the complement protect bit (cmp sr2[6]) is a non-volatile read / write bit in the status register (sr2[6]). it is used in conju nction with sec, tb, bp2, bp1 and bp0 bits to provi de more flexibility for the array protection. once cmp is set to 1, previous array protection set by sec, tb, bp2, bp1 and bp0 will be reversed. fo r instance, when cmp= 0, a top 4-kb sector can be protected while the rest of the array is not; when cm p=1, the top 4-kb sector will become unpr otected while the rest of the array become read- only. refer to section 6.5.7, block protection maps on page 53 for details. the default setting is cmp=0.
document number: 002-00497 rev. *e page 53 of 90 s25FL116K, s25fl132k, s25fl164k 6.5.7 block protection maps notes: 1. x = don?t care. 2. if any erase or program comm and specifies a memory region that contains protected data portion, this command will be ignored. table 6.11 FL116K block protection (cmp = 0) status register (1) s25fl1-k (16 mbit) block protection (cmp=0) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 none none none none 0 0 0 0 1 31 1f0000h ? 1fffffh 64 kb upper 1/32 0 0 0 1 0 30 and 31 1e0000h ? 1fffffh 128 kb upper 1/16 0 0 0 1 1 28 thru 31 1c0000h ? 1fffffh 256 kb upper 1/8 0 0 1 0 0 24 thru 31 180000h ? 1fffffh 512 kb upper 1/4 0 0 1 0 1 16 thru 31 100000h ? 1fffffh 1 mb upper 1/2 0 1 0 0 1 0 000000h ? 00ffffh 64 kb lower 1/32 0 1 0 1 0 0 and 1 000000h ? 01ffffh 128 kb lower 1/16 0 1 0 1 1 0 thru 3 000000h ? 03ffffh 256 kb lower 1/8 0 1 1 0 0 0 thru 7 000000h ? 07ffffh 512 kb lower 1/4 0 1 1 0 1 0 thru 15 000000h ? 0fffffh 1 mb lower 1/2 x x 1 1 x 0 thru 31 000000h ? 1fffffh 2 mb all 1 0 0 0 1 31 1ff000h ? 1fffffh 4 kb upper 1/512 1 0 0 1 0 31 1fe000h ? 1fffffh 8 kb upper 1/256 1 0 0 1 1 31 1fc000h ? 1fffffh 16 kb upper 1/128 1 0 1 0 x 31 1f8000h ? 1fffffh 32 kb upper 1/64 1 1 0 0 1 0 000000h ? 000fffh 4 kb lower 1/512 1 1 0 1 0 0 000000h ? 001fffh 8 kb lower 1/256 1 1 0 1 1 0 000000h ? 003fffh 16 kb lower 1/128 1 1 1 0 x 0 000000h ? 007fffh 32 kb lower 1/64 table 6.12 FL116K block protection (cmp = 1) status register (1) s25fl1-k (16 mbit) block protection (cmp=1) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 0 thru 31 000000h ? 1fffffh all all 0 0 0 0 1 0 thru 30 000000h ? 1effffh 1,984 kb lower 31/32 0 0 0 1 0 0 thru 29 000000h ? 1dffffh 1,920 kb lower 15/16 0 0 0 1 1 0 thru 27 000000h ? 1bffffh 1,792 kb lower 7/8 0 0 1 0 0 0 thru 23 000000h ? 17ffffh 1,536 kb lower 3/4 0 0 1 0 1 0 thru 15 000000h ? 0fffffh 1 mb lower 1/2 0 1 0 0 1 1 thru 31 010000h ? 1fffffh 1,984 kb upper 31/32 0 1 0 1 0 2 and 31 020000h ? 1fffffh 1,920 kb upper 15/16 0 1 0 1 1 4 thru 31 040000h ? 1fffffh 1,792 kb upper 7/8 0 1 1 0 0 8 thru 31 080000h ? 1fffffh 1,536 kb upper 3/4 0 1 1 0 1 16 thru 31 100000h ? 1fffffh 1 mb upper 1/2 x x 1 1 x none none none none 1 0 0 0 1 0 thru 31 000000h ? 1fefffh 2,044 kb lower 511/512
document number: 002-00497 rev. *e page 54 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. x = don?t care. 2. if any erase or program comm and specifies a memory region that contains protected data portion, this command will be ignored. notes: 1. x = don?t care. 2. if any erase or program comm and specifies a memory region that contains protected data portion, this command will be ignored. 1 0 0 1 0 0 thru 31 000000h ? 1fdfffh 2,040 kb lower 255/256 1 0 0 1 1 0 thru 31 000000h ? 1fbfffh 2,032 kb lower 127/128 1 0 1 0 x 0 thru 31 000000h ? 1f7fffh 2,016 kb lower 63/64 1 1 0 0 1 0 thru 31 001000h ? 1fffffh 2,044 kb upper 511/512 1 1 0 1 0 0 thru 31 002000h ? 1fffffh 2,040 kb upper 255/256 1 1 0 1 1 0 thru 31 004000h ? 1fffffh 2,032 kb upper 127/128 1 1 1 0 x 0 thru 31 008000h ? 1fffffh 2,016 kb upper 63/64 table 6.13 fl132k block protection (cmp = 0) status register (1) s25fl132k (32-mbit) block protection (cmp=0) () sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 none none none none 0 0 0 0 1 63 3f0000h ? 3fffffh 64 kb upper 1/64 0 0 0 1 0 62 and 63 3e0000h ? 3fffffh 128 kb upper 1/32 0 0 0 1 1 60 thru 63 3c0000h ? 3fffffh 256 kb upper 1/16 0 0 1 0 0 56 thru 63 380000h ? 3fffffh 512 kb upper 1/8 0 0 1 0 1 48 thru 63 300000h ? 3fffffh 1 mb upper 1/4 0 0 1 1 0 32 thru 63 200000h ? 3fffffh 2 mb upper 1/2 0 1 0 0 1 0 000000h ? 00ffffh 64 kb lower 1/64 0 1 0 1 0 0 and 1 000000h ? 01ffffh 128 kb lower 1/32 0 1 0 1 1 0 thru 3 000000h ? 03ffffh 256 kb lower 1/16 0 1 1 0 0 0 thru 7 000000h ? 07ffffh 512 kb lower 1/8 0 1 1 0 1 0 thru 15 000000h ? 0fffffh 1 mb lower 1/4 0 1 1 1 0 0 thru 31 000000h ? 1fffffh 2 mb lower 1/2 x x 1 1 1 0 thru 63 000000h ? 3fffffh 4 mb all 1 0 0 0 1 63 3ff000h ? 3fffffh 4 kb upper 1/1024 1 0 0 1 0 63 3fe000h ? 3fffffh 8 kb upper 1/512 1 0 0 1 1 63 3fc000h ? 3fffffh 16 kb upper 1/256 1 0 1 0 x 63 3f8000h ? 3fffffh 32 kb upper 1/128 1 1 0 0 1 0 000000h ? 000fffh 4 kb lower 1/1024 1 1 0 1 0 0 000000h ? 001fffh 8 kb lower 1/512 1 1 0 1 1 0 000000h ? 003fffh 16 kb lower 1/256 1 1 1 0 x 0 000000h ? 007fffh 32 kb lower 1/128 table 6.12 FL116K block protection (cmp = 1) (continued) status register (1) s25fl1-k (16 mbit) block protection (cmp=1) (2)
document number: 002-00497 rev. *e page 55 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. x = don?t care. 2. if any erase or program comm and specifies a memory region that contains protected data portion, this command will be ignored. table 6.14 fl132k block protection (cmp = 1) status register (1) s25fl132k (32-mbit) block protection (cmp=1) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 0 thru 63 000000h ? 3fffffh 4 mb all 0 0 0 0 1 0 thru 62 000000h ? 3effffh 4,032 kb lower 63/64 0 0 0 1 0 0 and 61 000000h ? 3dffffh 3,968 kb lower 31/32 0 0 0 1 1 0 thru 59 000000h ? 3bffffh 3,840 kb lower 15/16 0 0 1 0 0 0 thru 55 000000h ? 37ffffh 3,584 kb lower 7/8 0 0 1 0 1 0 thru 47 000000h ? 2fffffh 3 mb lower 3/4 0 0 1 1 0 0 thru 31 000000h ? 1fffffh 2 mb lower 1/2 0 1 0 0 1 1 thru 63 010000h ? 3fffffh 4,032 kb upper 63/64 0 1 0 1 0 2 and 63 020000h ? 3fffffh 3,968 kb upper 31/32 0 1 0 1 1 4 thru 63 040000h ? 3fffffh 3,840 kb upper 15/16 0 1 1 0 0 8 thru 63 080000h ? 3fffffh 3,584 kb upper 7/8 0 1 1 0 1 16 thru 63 100000h ? 3fffffh 3 mb upper 3/4 0 1 1 1 0 32 thru 63 200000h ? 3fffffh 2 mb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 thru 63 000000h ? 3fefffh 4,092 kb lower 1023/1024 1 0 0 1 0 0 thru 63 000000h ? 3fdfffh 4,088 kb lower 511/512 1 0 0 1 1 0 thru 63 000000h ? 3fbfffh 4,080 kb lower 255/256 1 0 1 0 x 0 thru 63 000000h ? 3f7fffh 4,064 kb lower 127/128 1 1 0 0 1 0 thru 63 001000h ? 3fffffh 4,092 kb upper 1023/1024 1 1 0 1 0 0 thru 63 002000h ? 3fffffh 4,088 kb upper 511/512 1 1 0 1 1 0 thru 63 004000h ? 3fffffh 4,080 kb upper 255/256 1 1 1 0 x 0 thru 63 008000h ? 3fffffh 4,064 kb upper 127/128 table 6.15 fl164k block protection (cmp = 0) status register (1) s25fl164k (64-mbit) block protection (cmp=0) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 none none none none 0 0 0 0 1 126 and 127 7e0000h ? 7fffffh 128 kb upper 1/64 0 0 0 1 0 124 thru 127 7c0000h ? 7fffffh 256 kb upper 1/32 0 0 0 1 1 120 thru 127 780000h ? 7fffffh 512 kb upper 1/16 0 0 1 0 0 112 thru 127 700000h ? 7fffffh 1 mb upper 1/8 0 0 1 0 1 96 thru 127 600000h ? 7fffffh 2 mb upper 1/4 0 0 1 1 0 64 thru 127 400000h ? 7fffffh 4 mb upper 1/2 0 1 0 0 1 0 and 1 000000h ? 01ffffh 128 kb lower 1/64 0 1 0 1 0 0 thru 3 000000h ? 03ffffh 256 kb lower 1/32 0 1 0 1 1 0 thru 7 000000h ? 07ffffh 512 kb lower 1/16
document number: 002-00497 rev. *e page 56 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. x = don?t care. 2. if any erase or program comm and specifies a memory region that contains protected data portion, this command will be ignored. 0 1 1 0 0 0 thru 15 000000h ? 0fffffh 1 mb lower 1/8 0 1 1 0 1 0 thru 31 000000h ? 1fffffh 2 mb lower 1/4 0 1 1 1 0 0 thru 63 000000h ? 3fffffh 4 mb lower 1/2 x x 1 1 1 0 thru 127 000000h ? 7fffffh 8 mb all 1 0 0 0 1 127 7ff000h ? 7fffffh 4 kb upper 1/2048 1 0 0 1 0 127 7fe000h ? 7fffffh 8 kb upper 1/1024 1 0 0 1 1 127 7fc000h ? 7fffffh 16 kb upper 1/512 1 0 1 0 x 127 7f8000h ? 7fffffh 32 kb upper 1/256 1 1 0 0 1 0 000000h ? 000fffh 4 kb lower1/2048 1 1 0 1 0 0 000000h ? 001fffh 8 kb lower 1/1024 1 1 0 1 1 0 000000h ? 003fffh 16 kb lower 1/512 1 1 1 0 x 0 000000h ? 007fffh 32 kb lower 1/256 table 6.16 fl164k block protection (cmp = 1) status register (1) s25fl164k (64-mbit) block protection (cmp=1) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion x x 0 0 0 0 thru 127 000000h ? 7fffffh 8 mb all 0 0 0 0 1 0 thru 125 000000h ? 7dffffh 8,064 kb lower 63/64 0 0 0 1 0 0 thru 123 000000h ? 7bffffh 7,936 kb lower 31/32 0 0 0 1 1 0 thru 119 000000h ? 77ffffh 7,680 kb lower 15/16 0 0 1 0 0 0 thru 111 000000h ? 6fffffh 7 mb lower 7/8 0 0 1 0 1 0 thru 95 000000h ? 5fffffh 5 mb lower 3/4 0 0 1 1 0 0 thru 63 000000h ? 3fffffh 4 mb lower 1/2 0 1 0 0 1 2 thru 127 020000h ? 7fffffh 8,064 kb upper 63/64 0 1 0 1 0 4 thru 127 040000h ? 7fffffh 7,936 kb upper 31/32 0 1 0 1 1 8 thru 127 080000h ? 7fffffh 7,680 kb upper 15/16 0 1 1 0 0 16 thru 127 100000h ? 7fffffh 7 mb upper 7/8 0 1 1 0 1 32 thru 127 200000h ? 7fffffh 5 mb upper 3/4 0 1 1 1 0 64 thru 127 400000h ? 7fffffh 4 mb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 thru 127 000000h ? 7fefffh 8,188 kb lower 2047/2048 1 0 0 1 0 0 thru 127 000000h ? 7fdfffh 8,184 kb lower 1023/1024 1 0 0 1 1 0 thru 127 000000h ? 7fbfffh 8,176 kb lower 511/512 1 0 1 0 x 0 thru 127 000000h ? 7f7fffh 8,160 kb lower 255/256 1 1 0 0 1 0 thru 127 001000h ? 7fffffh 8,188 kb lower 2047/2048 table 6.15 fl164k block protection (cmp = 0) (continued) status register (1) s25fl164k (64-mbit) block protection (cmp=0) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion
document number: 002-00497 rev. *e page 57 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. x = don?t care. 2. if any erase or program comm and specifies a memory region that contains protected data portion, this command will be ignored. 6.5.8 status register protect (srp1, srp0) the status register protect bits (srp1 and srp0) are non-volatile read / write bits in the status register (sr2[0] and sr1[7]). the srp bits control the method of write protec tion: software protection, hardware protection, power supply lock-down, or one time programmable (otp) protection. notes: 1. when srp1, srp0 = (1, 0), a power-down, power-up, or software reset cycle will change srp1, srp0 to (0, 0) state. 2. the one-time program feature is available up on special order. contact spansion for details. 3. busy, wel, and sus (sr1[1:0] and sr2[7]) are volatile read only st atus bits that are never affected by the write status regis ters command. 4. the non-volatile version of cmp, qe, srp1, srp0, sec, tb, and bp2-bp0 (sr2[6,1,0] and sr1[6:2]) bits and the otp lb3-lb0 bits are not writable when protected by the srp bits and wp# as shown in the table. the non-volatile version of these status register bits are selected for writing when the write enable (06h) command precedes the write status registers (01h) command. 5. the volatile version of cmp, qe, srp1, srp0, sec, tb, and bp2- bp0 (sr2[6,1,0] and sr1[6:2]) bits are not writable when protec ted by the srp bits and wp# as shown in the table. the volatile version of these status regist er bits are selected for writing when the write enable for volat ile status register (50h) command precedes the write status registers (01h) command. there is no vo latile version of the lb3-lb0 bits and these bits are not affe cted by a volatile write status registers command. 6. the volatile sr3 bits are not protected by the srp bits and ma y be written at any time by volatile (50h) write enable command preceding the write status registers (01h) command. 6.5.9 erase / program suspend status (sus) the suspend status bit is a read only bit in the status register (sr2[7]) that is set to 1 af ter executing an erase / program s uspend (75h) command. the sus status bit is cleared to 0 by erase / program resume (7ah) command as well as a power-down, power-up cycle. 6.5.10 security register lock bits (lb3, lb2, lb1, lb0) the security register lock bits (lb3, lb2, lb1, lb0) are non-vol atile one time program (otp) bits in status register (sr2[5:2]) that provide the write protect control and st atus to the security registers. the defaul t state of lb[3:1] is 0, security regist ers 1 to 3 are unlocked. lb[3:1] can be set to 1 individually using the wr ite status registers command. lb[3:1] are one time programmable (otp), once it?s set to 1, the corresponding 256-byte security register will become read-only permanently. security register 0 is programmed with the sfdp parameters and lb0 is programmed to 1 by cypress. 1 1 0 1 0 0 thru 127 002000h ? 7fffffh 8,184 kb lower 1023/1024 1 1 0 1 1 0 thru 127 004000h ? 7fffffh 8,176 kb lower 511/512 1 1 1 0 x 0 thru 127 008000h ? 7fffffh 8,160 kb lower 255/256 table 6.17 status register protection bits srp1 srp0 wp# status register description 0 0 x software protection wp# pin has no control. sr1 and sr2 can be written to after a write enable command, wel=1. [factory default] 0 1 0 hardware protected when wp# pin is low the sr1 and sr2 are locked and can not be written. 0 1 1 hardware unprotected when wp# pin is high sr1 and sr2 are unlocked and can be written to after a write enable command, wel=1. 10x power supply lock- down sr1 and sr2 are protected and can not be written to again until the next power-down, power-up cycle. (1) 1 1 x one time program (2) sr1 and sr2 are permanently prot ected and can not be written. table 6.16 fl164k block protection (cmp = 1) (continued) status register (1) s25fl164k (64-mbit) block protection (cmp=1) (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion
document number: 002-00497 rev. *e page 58 of 90 s25FL116K, s25fl132k, s25fl164k 6.5.11 quad enable (qe) the quad enable (qe) bit is a non-volatile read / write bit in t he status register (sr2 [1]) that allows quad spi operation. whe n the qe bit is set to a 0 state (factory default ), the wp# pin and hold# are enabled. when the qe bit is set to a 1, the quad io2 an d io3 pins are enabled, and wp# and hold# functions are disabled. note : if the wp# or hold# pins are tied directly to the power supply or ground during standard spi or dual spi operation, the qe bit should never be set to a 1. 6.5.12 latency control (lc) status register-3 provides bits (sr3[3:0]) to select the number of read latency cycl es used in each fast read command. the read data command is not af fected by the laten cy code. the binary val ue of this field selects from 1 to 15 latency cycles. the zero value selects the legacy number of latency cycles used in prior generation fl-k family devic es. the default is 0 cycles to provide backward compatibility to legacy devices. the latency control bits may be set to select a number of read cycles optimized for t he frequency in use. if the number of lat ency cycles is not sufficient for the operating frequency, invalid data will be read. notes: 1. sck frequency > 108 mhz sio, 108 mhz dio, or 108 mhz qi o is not supported by this family of devices. 2. the dual i/o and quad i/o command protocols include continuous read mode bits following the address. the clock cycles for the se bits are not counted as part of the latency cycles shown in the table. example: the legacy dual i/o command has four continuous read mode bits following the addres s and no additional dummy cycles. therefore, the legacy dual i/o command without additional read latency is supported only up to the frequency shown in the table for a read latency of zero cycles. by increasing the variable read latency the frequency of the dual i/o command can be increased to allow operation up to the maximu m supported 108 mhz dio frequency. table 6.18 latency cycles versus frequency for -40c to 85c/105c at 2.7v to 3.6v latency control read command maximum frequency (mhz) fast read dual output dual i/o quad output quad i/o 0 (legacy read latency) 108 (8 dummy) 108 (8 dummy) 88 (4 mode, 0 dummy) 108 (8 dummy) 78 (2 mode, 4 dummy) 1 5050944349 2 95 85 105 56 59 3 105 95 108 70 69 4 108 105 108 83 78 5 108 108 108 94 86 6 108 108 108 105 95 7 108 108 108 108 105 8 108 108 108 108 108 9 108 108 108 108 108 10 108 108 108 108 108 11 108 108 108 108 108 12 108 108 108 108 108 13 108 108 108 108 108 14 108 108 108 108 108 15 108 108 108 108 108
document number: 002-00497 rev. *e page 59 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. sck frequency > 97 mhz sio, 97 mhz dio, or 97 mhz qio (50 mhz for 16 mbit and 70 mhz for 32 mbit) at 2.6v at 125c is not sup ported by this family of devices. 2. the dual i/o and quad i/o command protocols include continuous read mode bits following the address. the clock cycles for the se bits are not counted as part of the latency cycles shown in the table. example: the legacy dual i/o command has four continuous read mod e bits following the address and no additional dummy cycles. therefore, the legacy dual i/o command without additional read latency is supported only up to the frequency shown in the table for a read latency of zero cycles. by increasing the variable read latency the freq uency of the dual i/o command can be increased to allow operation up to the maximum supported 97 mhz dio frequency. 6.5.13 burst wrap enable (w4) status register-3 provides a bit (sr3[4]) to enable a read with wrap option for the quad i/o read command. when sr3[4]=1, the wrap mode is not enabled and unlimited length sequential read is performed. when sr3[4]=0, the wrap mode is enabled and a fixed length and aligned group of 8, 16, 32, or 64 bytes will be read starting at the byte address provided by the quad i/o read comm and and wrapping around at the group alignment boundary. 6.5.14 burst wrap length (w6, w5) status register-3 provides bits (sr3[1:0]) to select the alignment boundary at which reading will wrap to perform a cache line fill. reading begins at the initial byte address of a fast read quad io command, then sequential bytes are read until the selected boundary is reached. reading then wraps to the beginning of the selected boundary. this enables critical word first cache line refills. the wrap point can be aligned on 8-, 16-, 32-, or 64-byte boundaries. table 6.19 latency cycles versus frequency fo r -40c to 125c at 2.6v to 3.6v latency control read command maximum frequency (mhz) fast read dual output dual i/o quad output quad i/o quad i/o at 125c at 2.7v quad i/o at 125c at 2.6v (16 / 32 / 64 mb) 0 (legacy read latency) 97 (8 dummy) 97 (8 dummy) 77 (4 mode, 0 dummy) 97 (8 dummy) 67 (2 mode, 4 dummy) 67 20/40/67 1 39398332 38 380/11/38 2 84749445 48 481/21/48 3 94849759 58 5811/31/58 4 97 94 97 72 67 67 20/40/67 5 97 97 97 83 75 75 28/48/75 6 97 97 97 94 84 84 37/57/84 7 97 97 97 97 94 94 47/67/94 8 97 97 97 97 97 97 50/70/97 9 97 97 97 97 97 97 50/70/97 10 97 97 97 97 97 97 50/70/97 11 97 97 97 97 97 97 50/70/97 12 97 97 97 97 97 97 50/70/97 13 97 97 97 97 97 97 50/70/97 14 97 97 97 97 97 97 50/70/97 15 97 97 97 97 97 97 50/70/97
document number: 002-00497 rev. *e page 60 of 90 s25FL116K, s25fl132k, s25fl164k 6.6 device identification 6.6.1 legacy device identification commands three legacy commands are supported to access device identification that can indicate the manufacturer, device type, and capaci ty (density). the returned data bytes provide the information as shown in table 6.20 . note: 1. the 90h instruction is followed by an address. address = 0 sele cts manufacturer id as the first returned data as shown in the table. address = 1 selects device id as the first returned data followed by manufacturer id. 6.6.2 serial flash discove rable parameters (sfdp) a read sfdp (5ah) command to read a jedec standard (jesd216) defined device information structure is supported. the information is stored in security register 0 and described in security register 0 ? serial flash discoverable parameters (sfdp ? jedec jesd216b) on page 40 . table 6.20 device identification device opn instruction data 1 data 2 data 3 s25FL116K abh device id = 14h ? ? 90h manufacturer id = 01h device id = 14h ? 9fh manufacturer id = 01h device type = 40h capacity = 15h s25fl132k abh device id = 15h ? ? 90h manufacturer id = 01h device id = 15h ? 9fh manufacturer id = 01h device type = 40h capacity = 16h s25fl164k abh device id = 16h ? ? 90h manufacturer id = 01h device id = 16h ? 9fh manufacturer id = 01h device type = 40h capacity = 17h
document number: 002-00497 rev. *e page 61 of 90 s25FL116K, s25fl132k, s25fl164k 7. functional description 7.1 spi operations 7.1.1 standard spi commands the s25fl1-k is accessed through an spi compatible bus consisting of four signals: serial clock (s ck), chip select (cs#), seria l data input (si) and serial data output (s o). standard spi commands use the si input pi n to serially write instructions, address es or data to the device on the rising edge of sck. the so output pin is used to read data or status from the device on the falling e dge sck. spi bus operation mode 0 (0,0) and 3 (1,1) are supported. the primary difference betw een mode 0 and mode 3 concerns the normal state of the sck signal when the spi bus mast er is in standby and data is not being transferred to the serial flash. for mode 0 , the sck signal is normally low on the falling and rising edges of cs#. for mode 3, the sck signal is normally high on the falling a nd rising edges of cs#. 7.1.2 dual spi commands the s25fl1-k supports dual spi operation when using the ?fas t read dual output (3bh)? and ?fast read dual i/o (bbh)? commands. these commands allow data to be transferred to or from t he device at two to three times the rate of ordinary serial f lash devices. the dual spi read commands are ideal for quickly downloading code to ram upon power-up (code-shadowing) or for executing non-speed-critical code directly from the spi bus (xip). when using dual spi commands, the si and so pins become bidirectional i/o pins: io0 and io1. 7.1.3 quad spi commands the s25fl1-k supports quad spi operatio n when using the ?fast read quad output (6bh)?, and ?fast read quad i/o (ebh)? commands. these commands allow data to be transferred to or from the device four to six times the rate of ordinary serial flash . the quad read commands offer a significant improvement in contin uous and random access transfer rates allowing fast code- shadowing to ram or execution directly from the spi bus (xip). when using quad spi commands the si and so pins become bidirectional io0 and io1, and the wp# an d hold# pins become io2 and io3 respectively. quad spi commands require the non- volatile or volatile quad enable bit (qe) in status register-2 to be set. 7.1.4 hold function for standard spi and dual spi operations, t he hold# (io3) signal allows the device inte rface operation to be paused while it is actively selected (when cs# is low). the hold function may be useful in cases where the spi data and clock signals are shared w ith other devices. for example, if the page buffer is only partially written when a priority interrupt requires use of the spi bus, the hold function can save the state of the interfac e and the data in the buffer so programming command can resume where it left off onc e the bus is available again. the hold function is only availabl e for standard spi and dual spi operation, not during quad spi. to initiate a hold condition, the device must be selected wit h cs# low. a hold condition will activate on the falling edge of t he hold# signal if the sck signal is already low. if the sck is not already low the hold condition will activate after the next fa lling edge of sck. the hold condition will terminate on the rising edge of t he hold# signal if the sck signal is already low. if the sck i s not already low the hold condition will terminate after the next falli ng edge of sck. during a hold condition, the serial data outp ut, (so) or io0 and io1, are high impedance and serial data input, (si) or io0 and io1, and serial clock (sck) are ignored. the chip sel ect (cs#) signal should be kept active (low) for the full duration of the hold operation to avoid resetting the internal logic stat e of the device.
document number: 002-00497 rev. *e page 62 of 90 s25FL116K, s25fl132k, s25fl164k 7.2 write protection applications that use non-volatile memory must take into consideration the possibility of noise and other ad verse system condit ions that may compromise data integrity. to address this concern, the s25fl1-k provides several means to protect the data from inadvertent program or erase. 7.2.1 write pr otect features ? device resets when v cc is below threshold ? time delay write disable after power-up ? write enable / disable commands and automatic write disable after erase or program ? command length protection ? all commands that write, program or eras e must complete on a byte boundary (cs# driven high after a full 8 bits have been clocked) otherwise the command will be ignored ? software and hardware write protec tion using status register control ? wp# input protection ? lock down write protection until next power-up or software reset ? one-time program (otp) write protection ? write protection using the deep power-down command upon power-up or at power-down, the s25fl1 -k will maintain a reset condition while v cc is below the threshold value of vwi, (see figure 4.5, power-up timing and voltage levels on page 24 ). while reset, all operations are disabled and no commands are recognized. during power-up and after the v cc voltage exceeds vwi, all program and erase related commands are further disabled for a time delay of t puw . this includes the write enable, page program, sector erase, block erase, chip erase and the write status registers commands. note that the chip select pin (cs#) must track the v cc supply level at power-up until the v cc -min level and t vsl time delay is reached. if needed a pull-up re sistor on cs# can be used to accomplish this. after power-up the device is autom atically placed in a write-di sabled state with the st atus register write enable latch (wel) s et to a 0. a write enable command must be issued before a page progra m, sector erase, block erase, chip erase or write status registers command will be accepted. after completing a program, erase or write co mmand the write enable latch (wel) is automatically cleared to a write-disabled state of 0. software controlled main flash array write protection is facili tated using the write status r egisters command to write the stat us register protect (srp0, srp1) and block pr otect (cmp, sec,tb, bp2, bp1 and bp0) bits. the bp method allows a portion as small as 4-kb sector or th e entire memory array to be configured as read only. used in conjunction with the write protect (wp#) pin, changes to the st atus register can be enabled or disabled under hardware control. see status registers on page 50. for further information. additionally, the deep power-down (dpd) command offers an alter native means of data pr otection as all commands are ignored during the dpd state, except for the release from deep-powe r-down (res abh) command. thus, preventing any program or erase during the dpd state. 7.3 status registers the read and write status registers co mmands can be used to provide status a nd control of the flash memory device.
document number: 002-00497 rev. *e page 63 of 90 s25FL116K, s25fl132k, s25fl164k 8. commands the command set of the s25fl1-k is fu lly controlled through the spi bus (see table 8.1 to table 8.4 on page 65 ). commands are initiated with the falling edge of ch ip select (cs#). the first byte of data cloc ked into the si input pr ovides the instruction code. data on the si input is sampled on the rising edge of clock with most significant bit (msb) first. commands vary in length from a single byte to several byte s. each command begins with an inst ruction code and may be followed by address bytes, a mode byte, read latency (dummy / don?t care ) cycles, or data bytes. commands are completed with the rising edge of edge cs#. clock relative sequence diagrams for each co mmand are included in the command descriptions. all read commands can be completed after any data bit. however, all command s that write, program or erase must complete on a byte boundary (cs# driven high after a full 8 bits have been clock ed) otherwise the command will be i gnored. this feature further pr otects the device from inadvertent writes. additi onally, while the memory is being programmed or erased, all commands except for read status register and suspend commands will be ignored until the program or erase cycle has completed. when the status register is being written, all commands except for read status register will be ignored until the status register write operation has completed. notes: 1. data bytes are shifted with most significant bit first. byte fields with data in brackets ?[]? indicate data being read from the device on the so pin. 2. status register contents will repeat continuously until cs# terminates the command. 3. set burst with wrap input format to load sr3. see table 6.10 on page 51 . io0 = x, x, x, x, x, x, w4, x] io1 = x, x, x, x, x, x, w5, x] io2 = x, x, x, x, x, x, w6 x] io3 = x, x, x, x, x, x, x,x 4. when changing the value of any single bit, read all other bits and rewrite the same value to them. table 8.1 command set (configuration, stat us, erase, program commands (1) ) command name byte 1 (instruction) byte 2 byte 3 byte 4 byte 5 byte 6 read status register-1 05h sr1[7:0] (2) (4) read status register-2 35h sr2[7:0] (2) (4) read status register-3 33h sr3[7:0] (2) write enable 06h write enable for volatile status register 50h write disable 04h write status registers 01h sr1[7:0] sr2[7:0] sr3[7:0] set burst with wrap 77h xxh xxh xxh sr3[7:0] (3) set block / pointer protection (s25fl132k / s25fl164k) 39h a23?a16 a15?a10, x, x xxh page program 02h a23?a16 a15?a8 a7?a0 d7?d0 sector erase (4 kb) 20h a23?a16 a15?a8 a7?a0 block erase (64 kb) d8h a23?a16 a15?a8 a7?a0 chip erase c7h / 60h erase / program suspend 75h erase / program resume 7ah
document number: 002-00497 rev. *e page 64 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2. dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3. quad output data io0 = (d4, d0, ?..) io1 = (d5, d1, ?..) io2 = (d6, d2, ?..) io3 = (d7, d3, ?..) 4. quad input address io0 = a20, a16, a12, a8, a4, a0, m4, m0 io1 = a21, a17, a13, a9, a5, a1, m5, m1 io2 = a22, a18, a14, a10, a6, a2, m6, m2 io3 = a23, a19, a15, a11, a7, a3, m7, m3 5. fast read quad i/o data io0 = (x, x, x, x, d4, d0, ?..) io1 = (x, x, x, x, d5, d1, ?..) io2 = (x, x, x, x, d6, d2, ?..) io3 = (x, x, x, x, d7, d3, ?..) 6. this command is recommended when using the dual or quad ?continuous read mode? feature. see section 8.4.3 and section 8.4.3 on page 76 for more information. notes: 1. this command is recommended when using the dual or quad ?continuous read mode? feature. see section 8.4.3 and section 8.4.3 on page 76 for more information. table 8.2 command set (read commands) command name byte 1 (instruction) byte 2 byte 3 byte 4 byte 5 byte 6 read data 03h a23?a16 a15?a8 a7?a0 (d7?d0, ?) fast read 0bh a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) fast read dual output 3bh a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) (1) fast read quad output 6bh a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) (3) fast read dual i/o bbh a23?a8 (2) a7?a0, m7? m0 (2) (d7?d0, ?) (1) fast read quad i/o ebh a23?a0, m7?m0 (4) (x,x,x,x, d7?d0, ?) (5) (d7?d0, ?) (3) continuous read mode reset (6) ffh ffh table 8.3 command set (reset commands) command name byte 1 (instruction) byte 2 byte 3 byte 4 byte 5 byte 6 software reset enable 66h software reset 99h continuous read mode reset (1) ffh ffh
document number: 002-00497 rev. *e page 65 of 90 s25FL116K, s25fl132k, s25fl164k notes: 1. the device id will repeat continuously until cs# terminates the command. 2. see section 6.6.1, legacy device identification commands on page 60 for device id information. the 90h instruction is followed by an address. address = 0 selects manufacturer id as the first returned data as shown in the table. address = 1 selects device id as the first returned data foll owed by manufacturer id. 3. security register address: security register 0: a23-16 = 00h; a15-8 = 00h; a7-0 = byte address security register 1: a23-16 = 00h; a15-8 = 10h; a7-0 = byte address security register 2: a23-16 = 00h; a15-8 = 20h; a7-0 = byte address security register 3: a23-16 = 00h; a15-8 = 30h; a7-0 = byte address security register 0 is used to store the sfdp parame ters and is always programmed and locked by spansion. 8.1 configuration and status commands 8.1.1 read status register s (05h), (35h), (33h) the read status register commands allow the 8-bit status regist ers to be read. the command is entered by driving cs# low and shifting the instruction code ?05h? for status register-1, ?35h? for status register-2, or 33h for status register-3, into the si pin on the rising edge of sck. the status register bits are then shifted out on the so pin at the falling edge of sck with most signif icant bit (msb) first as shown in figure 8.1 . the status register bits are shown in section 6.5, status registers on page 50 . the read status regist er-1 (05h) command may be used at any time, even while a program, eras e, or write stat us registers cycle is in progress. this allows the busy status bit to be checked to determine when the operation is complete and if the device can accept another command. the read status register-2 (35h), and read status registers (33h) may be used only when the device is in standby, not busy with an embedded operation. status registers can be read co ntinuously as each repeated data output delivers the updated curr ent value of each status regist er. example: using the instruction co de ?05h? for read status register-1, the first output of eight bits may show the device is bus y, sr1[0]=1. by continuing to hold cs# low, the updated value of sr1 will be shown in the next byte output. this repeated reading of sr1can continue until the system detects the busy bit has changed back to ready status in one of the status bytes being read ou t. the read status register commands are completed by driving cs# high. figure 8.1 read status register command sequence diagram for 05h and 35h table 8.4 command set (id, security commands) command name byte 1 (instruction) byte 2 byte 3 byte 4 byte 5 byte 6 deep power-down b9h release power down / device id abh dummy dummy dummy device id (1) manufacturer / device id (2) 90h dummy dummy 00h manufacturer device id jedec id 9fh manufacturer memory type capacity read sfdp register / read unique id number 5ah 00h 00h a7?a0 dummy (d7?d0, ?) read security registers (3) 48h a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) erase security registers (3) 44h a23?a16 a15?a8 a7?a0 program security registers (3) 42h a23?a16 a15?a8 a7?a0 d7?d0, ? cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction status updated status
document number: 002-00497 rev. *e page 66 of 90 s25FL116K, s25fl132k, s25fl164k figure 8.2 read status register-3 command sequence diagram for 33h ? s25fl132k / s25fl164k 8.1.2 write enable (06h) the write enable command ( figure 8.3 ) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, sector erase, block erase, chip erase, write status register s and erase / program security registers command. the write enable command is entered by driving cs# low, shifting the instruction code ?06h? into the data input (si) pin on the rising edge of sck, and then driving cs# high. figure 8.3 write enable (wren 06h) command sequence 8.1.3 write enable for volati le status register (50h) the non-volatile status register bits described in section 6.5, status registers on page 50 can also be written to as volatile bits. during power up reset, the non-volatile status register bits are copied to a volatile ve rsion of the status register that is us ed during device operation. this gives more flexibility to change the syst em configuration and memory pr otection schemes quickly without waiting for the typical non-volatile bit writ e cycles or affecting the endurance of the status register non-volatile bits. to w rite the volatile version of the status register bi ts, the write enable for vola tile status regist er (50h) command must be issued and immediately followed by the write status registers (01h) command. write enable fo r volatile status register command ( figure 8.4 ) will not set the write enable latch (wel) bit, it is only valid for the next following write st atus registers command, to chang e the volatile status register bit values. figure 8.4 write enable for volatile status register command sequence 8.1.4 write disable (04h) the write disable command resets the write enable latch (wel) bit in the status register to a 0. the write disable command is entered by driving cs# low, shifting the in struction code ?04h? into the si pin and then driving cs# high. note that the wel bi t is automatically reset after power-up and upon completion of the writ e status registers, erase / pr ogram security registers, page program, sector erase, block erase and chip erase commands. cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 23 22 21 20 11 10 9 8 instruction status pointer address cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00497 rev. *e page 67 of 90 s25FL116K, s25fl132k, s25fl164k figure 8.5 write disable (wrdi 04h) command sequence 8.1.5 write status registers (01h) the write status registers command allows th e status registers to be wri tten. only non-volatile status register bits srp0, sec, tb, bp2, bp1, bp0 (sr1[7:2]) cmp, lb3, lb2, lb1, qe, srp1 (sr2[6:0]), and the vola tile bits sr3[6:0] can be written. all other status register bit locations are read-only and will not be affected by t he write status registers co mmand. lb3-0 are non-volat ile otp bits; once each is set to 1, it can not be cleared to 0. the status register bits are shown in section 6.5, status registers on page 50 . any reserved bits should only be written to their default value. to write non-volatile status r egister bits, a standard write enable (06h) comm and must previously have been executed for the device to accept the write status register s command (status register bit wel must eq ual 1). once write enabled, the command is entered by driving cs# low, sending the instruction code ?01h?, and then writing the status register data bytes as illustrated in figure 8.6 . to write volatile status register bits, a write enable for volatile status register (50h) command must have been executed prior to the write status registers command (status register bit wel remains 0). however, srp1 and lb3, lb2, lb1, lb0 can not be changed because of the otp protection for these bits. upon power-o ff, the volatile status register bit values will be lost, and the non-volatile status register bit values will be restored when power on again. to complete the write status registers comm and, the cs# pin must be driven high after the eighth bit of a data value is clocked in (cs# must be driven high on an 8-bit boundary). if this is no t done the write status registers command will not be executed. if cs# is driven high after the eighth clock the cmp and qe bits will be cleared to 0 if the srp1 bit is 0. the sr2 bits are unaffecte d if srp1 is 1. if cs# is driven high afte r the eighth or sixteenth clock, the sr3 bits will not be affected. during non-volatile status register write operation (06h combined with 01h), after cs# is driven high at the end of the write s tatus registers command, the self-timed wr ite status registers operation will co mmence for a time duration of t w (see section 4.8, ac electrical characteristics on page 25 ). while the write status registers operation is in progress, the read status register command may still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status registers operat ion and a 0 when the operation is finished and ready to accept ot her commands again. after the wr ite status registers operation has finished, the write enable latch (wel) bit in the status register will be cleared to 0. during volatile status register write operation (50h combined with 01h), after cs# is driven high at the end of the write statu s registers command, the status register bits will be upda ted to the new values within the time period of t shsl2 (see section 4.8, ac electrical characteristics on page 25 ). busy bit will remain 0 during the status register bit refresh period. refer to section 6.5, status registers on page 50 for detailed status register bit descriptions. figure 8.6 write status registers command sequence diagram cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction input status register-1 input status register-2 input status register-3
document number: 002-00497 rev. *e page 68 of 90 s25FL116K, s25fl132k, s25fl164k 8.2 program and erase commands 8.2.1 page program (02h) the page program command allows from one byte to 256 bytes (a page) of data to be programme d at previously erased (ffh) memory locations. a write enable command must be executed before the device will accept the page program command (status register bit wel= 1). the command is initiated by driving the cs# pin low then shifting the inst ruction code ?02h? followed by a 24- bit address (a23-a0) and at least one data byte, into the si pin. the cs# pin must be held low for the entire length of the com mand while data is being sent to the device. the page program command sequence is shown in figure 8.7, page program command sequence on page 68 . if an entire 256-byte page is to be programmed, the last address by te (the 8 least significant address bits) should be set to 0 . if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the begin ning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without havi ng any effect on other bytes wit hin the same page. one condition to perform a partial page program is that the number of clocks can not exce ed the remaining page length. if more than 256 bytes ar e sent to the device the addressing will wrap to the beginning of the page and overwrite previ ously sent data. as with the write and erase commands, the cs# pin must be driven high after the eight h bit of the last byte has been latched. i f this is not done the page program command will not be executed. after cs# is driven high, the self-timed page program command will commence for a time duration of t pp ( section 4.8, ac electrical characteristics on page 25 ). while the page program cycle is in progress, the read status register command may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the page program cycle has finis hed the write enable latch (wel) bit in the status register is cleared to 0. the p age program command will not be executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits. figure 8.7 page program command sequence 8.2.2 sector erase (20h) the sector erase command sets all memory within a specified sect or (4 kbytes) to the erased state of all 1?s (ffh). a write ena ble command must be executed before the device will accept the sector erase command (sta tus register bit wel must equal 1). the command is initiated by driving the cs# pin low and shifting t he instruction code ?20h? follow ed a 24-bit sector address (a23-a 0) see supply and signal ground (v ss ) on page 10. the sector erase command sequence is shown in figure 8.8 on page 68 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase co mmand will not be executed. after cs# is driven high, the self-timed sector erase command will commence for a time duration of t se . section 4.8, ac electrical characteristics on page 25 while the sector erase cycle is in progress, the read status register command may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. th e sector erase command will not be executed if the addressed sector is protected by the blo ck protect (cmp, sec, tb, bp2, bp1, and bp0) bits ( table 6.13, fl132k block protection (cmp = 0) on page 54 ). figure 8.8 sector erase command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 23 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2 cs# sck si so phase 76 54321023 1 0 instruction address
document number: 002-00497 rev. *e page 69 of 90 s25FL116K, s25fl132k, s25fl164k 8.2.3 64-kb block erase (d8h) the block erase command sets all memory within a specified block ( 64 kbytes) to the erased state of all 1s (ffh). a write enabl e command must be executed before the device will accept the block erase command (status register bit wel must equal 1). the command is initiated by driving the cs# pin low and shifting the instruction code ?d8h? follo wed a 24-bit block address (a23-a0 ) see supply and signal ground (v ss ) on page 10. the block erase command sequence is shown in figure 8.9 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase com mand will not be executed. after cs# is driven high, the self-timed block erase co mmand will commence for a time duration of t be (see section 4.8, ac electrical characteristics on page 25 ). while the block erase cycle is in progress, the read status register command may still be accessed for checking the status of the busy bit. the busy bi t is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase command will not be executed if the addressed sector is protected by the block prot ect (cmp, sec, tb, bp2, bp1, and bp0) bits (see section 6.5, status registers on page 50 ). figure 8.9 64-kb block erase command sequence 8.2.4 chip erase (c7h / 60h) the chip erase command sets all memory within the device to th e erased state of all 1?s (ffh). a write enable command must be executed before the device will accept the ch ip erase command (status register bit we l must equal 1). the command is initiated by driving the cs# pin low and shifting the instruction code ?c 7h? or ?60h?. the chip erase command sequence is shown in figure 8.10 . the cs# pin must be driven high after the eighth bit has been latc hed. if this is not done the chip erase command will not be executed. after cs# is driven high, the self-timed chip erase command will commence for a time duration of t ce ( section 4.8, ac electrical characteristics on page 25 ). while the chip erase cycle is in progress, the read status register command may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other commands again. after t he chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase command will not be executed if any page is protected by the block protect (cmp , sec, tb, bp2, bp1, and bp0) bits (see section 6.5, status registers on page 50 ). figure 8.10 chip erase command sequence cs# sck si so phase 76 54321023 1 0 instruction address cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00497 rev. *e page 70 of 90 s25FL116K, s25fl132k, s25fl164k 8.2.5 erase / program suspend (75h) the erase / program suspend command allows the system to inte rrupt a sector or block eras e operation, then read from or program data to any other sector. the erase / program suspend command also allows the system to interrupt a page program operation and then read from any other page or erase any other sector or block. t he erase / program suspend command sequence is shown in figure 8.11, erase / program suspend command sequence on page 70 . the write status registers command (01h), program security regi sters (42h), and erase commands (20h, d8h, c7h, 60h, 44h) are not allowed during erase suspend. erase suspend is valid only du ring the sector or block erase operation. if written during the chip erase operation, the erase suspend command is ignored. the write status registers command (01h), erase security registers (44h), and program commands (02h, 32h, 42h) are not allowed dur ing program suspend. program suspend is valid only during the page program operation. the erase / program suspend command 75h will be accepted by the device only if the sus bit in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase or a page program operation is on-going. if the sus bit equals to 1 or the busy bit equals to 0, the suspend command will be ignored by the device. program or erase command for the sector that is being suspended will be ignored. a maximum of time of t sus ( section 4.8, ac electrical characteristics on page 25 ) is required to suspend the erase or program operation. the busy bit in the status regist er will be cleared from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately after erase / program suspend. for a pr eviously resumed erase / program operation, it is also requi red that the suspend command 75h is not issu ed earlier than a minimum of time of t sus following the preceding resume command 7ah. unexpected power off during the erase / program suspend state will reset the device and release the suspend state. sus bit in t he status register will also reset to 0. t he data within the page, sector or block that was being suspended may become corrupted. it is recommended for the user to implement syst em design techniques to prevent accidental power interruption, provide non-volatile tracking of in process program or erase commands, and preserve data integrity by evaluating th e non-volatile program or erase tracking information during each system power up in order to identify and repair (re-erase and re-program) any improperly terminated program or erase operations. figure 8.11 erase / program suspend command sequence table 8.5 commands accepted during suspend operation suspended command allowed instruction program or erase read data 03h program or erase fast read 0bh program or erase fast read dual output 3bh program or erase fast read quad output 6bh program or erase fast read dual i/o bbh program or erase fast read quad i/o ebh program or erase continuous read mode reset ffh program or erase read status register-1 05h program or erase read status register-2 35h program or erase write enable 06h erase page program 02h program sector erase 20h program block erase d8h program or erase erase / program resume 7ah cs# sck si so phase phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 suspend instruction read status instruction status instr. during suspend repeat status read until suspended t sus
document number: 002-00497 rev. *e page 71 of 90 s25FL116K, s25fl132k, s25fl164k 8.2.6 erase / program resume (7ah) the erase / program resume command ?7ah? must be written to re sume the sector or block eras e operation or the page program operation after an erase / program suspend. the resume command ?7ah ? will be accepted by the device only if the sus bit in the status register equals to 1 and the busy bit equals to 0. afte r the resume command is issued the sus bit will be cleared from 1 to 0 immediately, the busy bit will be set from 0 to 1 within 200 ns and the sector or block will co mplete the erase operation or the page will complete the program operation. if the sus bit equals to 0 or the busy bit equals to 1, the resume command ?7ah? will be ignored by the device. the erase / program resume command sequence is shown in figure 8.12 . it is required that a subsequent erase / program suspend command not to be issued within a minimum of time of ?t sus ? following a resume command. figure 8.12 erase / program resume command sequence 8.3 read commands 8.3.1 read data (03h) the read data command allows one or more data bytes to be se quentially read from the memory. the command is initiated by driving the cs# pin low and then shifting the instruction code ?0 3h? followed by a 24-bit address (a23-a0) into the si pin. the code and address bits are latched on the rising edge of the sck pin. after the address is received, the data byte of the addressed m emory location will be shifted out on the so pin at the falling edge of sck with most significant bit (msb) first. the address is aut omatically incremented to the next higher address after ea ch byte of data is shifted out allowing fo r a continuous stream of data. this me ans that the entire memory can be accessed with a single command as long as the clock continues. the command is completed by driving cs# high. the read data command sequence is shown in figure 8.13 . if a read data command is issued while an erase, program or write cycle is in process (busy=1) the command is ignored and will not have any effects on the current cycle. the read data command allows clock rates from dc to a maximum of f r (see section 4.8, ac electrical characteristics on page 25 ). figure 8.13 read data command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address data 1 data 2
document number: 002-00497 rev. *e page 72 of 90 s25FL116K, s25fl132k, s25fl164k 8.3.2 fast read (0bh) the fast read command is similar to the read data command except that it can operate at higher frequency than the traditional read data command. this is accomplished by adding eight ?dummy? clo cks after the 24-bit address as shown in figure 8.14 . the dummy clocks allow the devices inte rnal circuits additio nal time for setting up the initia l address. during the dummy clocks th e data value on the si pin is a ?don?t care.? when variable read latency is ena bled, the number of dummy cycles is set by the latency control value in sr3 to optimize the latency for the frequency in use. see. table 6.18, latency cycles versus frequency for -40c to 85c/105c at 2.7v to 3.6v on page 58 . figure 8.14 fast read command sequence 8.3.3 fast read dual output (3bh) the fast read dual output (3bh) command is similar to the standar d fast read (0bh) command except that data is output on two pins; io0 and io1. this allows data to be transferred from the s 25fl1-k at twice the rate of standard spi devices. the fast rea d dual output command is ideal for quickly downloading code from flash to ram upon power-up or for applications that cache code- segments to ram for execution. similar to the fast read command, the fast read dual output command can operate at higher fr equency than the traditional read data command. this is accomplished by adding eight ?d ummy? clocks after the 24-bit address as shown in figure 8.15 . the dummy clocks allow the device's internal circuits additional time fo r setting up the initial address. the input data during the dummy clocks is ?don?t care.? however, the io0 pin should be high-impe dance prior to the falling edge of the first data out clock. when variable read latency is ena bled, the number of dummy cycles is set by the latency control value in sr3 to optimize the latency for the frequency in use. see. table 6.18, latency cycles versus frequency for -40c to 85c/105c at 2.7v to 3.6v on page 58 . figure 8.15 fast read dual output command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 23 22 21 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 instruction address dummy data 1 data 2
document number: 002-00497 rev. *e page 73 of 90 s25FL116K, s25fl132k, s25fl164k 8.3.4 fast read quad output (6bh) the fast read quad output (6bh) command is similar to the fast read dual output (3bh) command except that data is output on four pins, io0, io1, io2, and io 3. a quad enable of status regist er-2 must be executed before the device will accept the fast r ead quad output command (status register bit qe must equal 1). th e fast read quad output command allows data to be transferred from the s25fl1-k at four times the rate of standard spi devices. the fast read quad output command can operate at higher frequency than the traditional read data command. this is accomplished by adding eight ?dummy? clo cks after the 24-bit address as shown in figure 8.16 . the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data du ring the dummy clocks is ?don?t care.? however, the io pins should be high-impedance prio r to the falling edge of the first data out clock. when variable read latency is ena bled, the number of dummy cycles is set by the latency control value in sr3 to optimize the latency for the frequency in use. see. table 6.18, latency cycles versus frequency for -40c to 85c/105c at 2.7v to 3.6v on page 58 . figure 8.16 fast read quad output command sequence 8.3.5 fast read dual i/o (bbh) the fast read dual i/o (bbh) command allows for improved random access while maintaining two io pins, io0 and io1. it is simila r to the fast read dual output (3bh) command but with the capabili ty to input the address bits (a23-0) two bits per clock. this reduced command overhead may allow for code execution (xip ) directly from the dual spi in some applications. fast read dual i/o with ?continuous read mode? the fast read dual i/o command can further reduce instruction overhead through setting the ?continuous read mode? bits (m7-0) after the input address bits (a23-0), as shown in figure 8.17 . the upper nibble of the (m7-4) cont rols the length of the next fast read dual i/o command through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3-0 ) are don?t care (?x?). however, the io pins should be high-im pedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5-4 = (1,0 ), then the next fast read dual i/o comm and (after cs# is raised and then lowered ) does not require the bbh instruction code, as shown in figure 8.18 . this reduces the command sequence by eight clocks and allows the read address to be immediately entered after cs# is asserted lo w. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next command (after cs# is rais ed and then lowered) requires the first byte instruction code, thus returning to norm al operation. a ?continuous read mode? reset command can also be used to reset (m7-0) before issuing normal commands (see see continuous read mode reset (ffh or ffffh) on page 76. ). when variable read latency is enabled, the number of latency (m ode + dummy) cycles is set by the latency control value in sr3 t o optimize the latency for the frequency in use. see table 6.18, latency cycles versus frequency for -40c to 85c/105c at 2.7v to 3.6v on page 58 . note that the legacy read dual i/o command has four mode cycles and no dummy cycles for a total of four latency cycles, enabling the variable read latency allows for the addition of more read latency to enable higher frequency oper ation of the dual i/o command. cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 23 1 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 instruction address dummy d1 d2 d3 d4 d5
document number: 002-00497 rev. *e page 74 of 90 s25FL116K, s25fl132k, s25fl164k figure 8.17 fast read dual i/o command sequence (initial command or previous m5-4 ? 10) note: 1. least significant 4 bits of mode are don?t care and it is op tional for the host to drive thes e bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. figure 8.18 fast read dual i/o command sequence (previous command set m5-4 = 10) 8.3.6 fast read quad i/o (ebh) the fast read quad i/o (ebh) command is simi lar to the fast read dual i/o (bbh) command except that addre ss and data bits are input and output through four pins io0, io 1, io2 and io3 and four dummy clock are requ ired prior to the data output. the quad i /o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. th e quad enable bit (qe) of status register-2 must be set to enable the fast read quad i/o command. fast read quad i/o with ?continuous read mode? the fast read quad i/o command can further reduce instruction overhead through setting the ?continuous read mode? bits (m7-0) after the input address bits (a23-0), as shown in figure 8.19, fast read quad i/o command sequence (initial command or previous m5-4 ? 10) on page 75 . the upper nibble of the (m7-4) controls the length of the next fast read quad i/o command through the inclusion or exclusion of the first byte instructi on code. the lower nibble bits of the (m3-0) are don?t care (?x?) . however, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5-4 = (1,0), then the next fast read quad i/o command (after cs# is raised and then lowered ) does not require the ebh inst ruction code, as shown in figure 8.20, fast read quad i/o command sequence (previous command set m5-4 = 10) on page 75 . this reduces the command sequence by eight clocks and allows the read address to be immediately entered after cs# is asserted low. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next command (after cs# i s raised and then lowered) requires the first byte instruction c ode, thus returning to normal operation. a ?continuous read mode? reset command can also be us ed to reset (m7-0) before issuing normal commands (see section 8.4.3, continuous read mode reset (ffh or ffffh) on page 76 ). when variable read latency is enabled, the number of latency (m ode + dummy) cycles is set by the latency control value in sr3 t o optimize the latency for the frequency in use. see. table 6.18, latency cycles versus frequency for -40c to 85c/105c at 2.7v to 3.6v on page 58 . note that the legacy read quad i/ o command has two mode cycl es plus four dummy cycles for a total of six latency cycles, enabling the variable read latency allows for the addition of more read latency to enable higher frequency oper ation of the quad i/o command. cs# sck io0 io1 phase 7 6 5 4 3 2 1 0 22 2 0 6 4 2 0 6 4 2 0 6 4 2 0 23 3 1 7 5 3 1 7 5 3 1 7 5 3 1 instruction address mode dummy data 1 data 2 cs# sck io0 io1 phase 6 4 2 0 22 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 23 3 1 7 5 3 1 7 5 3 1 7 5 3 1 data n address mode dummy data 1 data 2
document number: 002-00497 rev. *e page 75 of 90 s25FL116K, s25fl132k, s25fl164k figure 8.19 fast read quad i/o command sequence (initial command or previous m5-4 ? 10) note: 1. least significant 4 bits of mode are don?t care and it is op tional for the host to drive thes e bits. the host may turn off dr ive during these cycles to increase bus turn around time between mode bits from host and returning data from the memory. figure 8.20 fast read quad i/o command sequence (previous command set m5-4 = 10) fast read quad i/o with ?16 / 32 / 64-byte wrap around? the fast read quad i/o command can also be used to access a s pecific portion within a page by issuing a ?set burst with wrap? command prior to ebh. the ?set bu rst with wrap? command can either enable or disable the ?wrap around? feature for the followin g ebh commands. when ?wrap around? is enabled, the data being acce ssed can be limited to either a 16 / 32 / 64-byte section of data. the output data starts at the initial address specified in the command, once it reaches the ending boundary of the 16 / 3 2 / 64- byte section, the output will wrap around to the beginning bounda ry automatically until cs# is pulled high to terminate the com mand. the burst with wrap feature allows applicatio ns that use cache to quickly fetch a critic al address and then fill the cache afte rwards within a fixed length (16 / 32 / 64-bytes) of data without issuing multiple read commands. the ?set burst with wrap? command allows thr ee ?wrap bits?, w6-4 to be set. the w4 bit is used to enable or disable the ?wrap around? operation while w6-5 are us ed to specify the length of the wrap around section within a page. see section 8.3.7, set burst with wrap (77h) on page 75 . 8.3.7 set burst with wrap (77h) the set burst with wrap (77h) command is used in conjunction wi th ?fast read quad i/o? commands to access a fixed length and alignment of 8 / 16 / 32 / 64-bytes of dat a. certain applications can benefit from this feature an d improve the overall system code execution performance. this command loads the sr3 bits. similar to a quad i/o command, the set burst with wrap command is initiated by driving the cs# pin low and then shifting the instruction code ?77h? followed by 24-dummy bits and 8 ?wrap bits?, w7-0. the command sequence is shown in figure 8.21, set burst with wrap command sequence on page 76 . wrap bit w7 and the lower nibble w3-0 are not used. see status register-3 (sr3[6:4]) for the encoding of w6-w4 in section 6.5, status registers on page 50 . once w6-4 is set by a set burst with wrap command, all the foll owing ?fast read quad i/o? commands will use the w6-4 setting to access the 8 / 16 / 32 / 64-byte section of data. note, status regi ster-2 qe bit (sr2[1]) must be set to 1 in order to use the fast read quad i/o and set burst with wrap commands. to exit the ?w rap around? function and return to normal read operation, another set burst with wrap command should be issued to set w4 = 1. the default value of w4 upon power on is 1. in the case of a system reset while w4 = 0, it is recomme nded that the controll er issues a software reset co mmand or a set burst with wrap command to reset w4 = 1 prior to any normal read commands since s25fl1-k does not have a hardware reset pin. cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 20 4 0 4 0 4 0 4 0 4 0 4 0 21 5 1 5 1 5 1 5 1 5 1 5 1 22 6 2 6 2 6 2 6 2 6 2 6 2 23 7 3 7 3 7 3 7 3 7 3 7 3 instruction address mode dummy d1 d2 d3 d4 cs# sck io0 io1 io2 io3 phase 4 0 4 0 20 4 0 4 0 4 0 4 0 6 4 2 0 5 1 5 1 21 5 1 5 1 5 1 5 1 7 5 3 1 6 2 6 2 22 6 2 6 2 6 2 6 1 7 5 3 1 7 3 7 3 23 7 3 7 3 7 3 7 1 7 5 3 1 dn-1 dn address mode dummy d1 d2 d3 d4
document number: 002-00497 rev. *e page 76 of 90 s25FL116K, s25fl132k, s25fl164k figure 8.21 set burst with wrap command sequence 8.4 reset commands software controlled reset commands restore t he device to its initial power up state, by reloading volatile registers from non-v olatile default values. if a software reset is initiated during a erase, program or writing of a register operation the data in that se ctor, page or register is not stable, the operation that was interrupted needs to be initiated again. when the device is in deep power-down mode it is protected fr om a software reset, the software reset commands are ignored and have no effect. to reset the device send the release power down command (abh) and after time duration of t res1 the device will resume normal operation and the software reset commands will be accepted. a software reset is initiated by the software reset enable co mmand (66h) followed by software reset command (99h) and then executed when cs# is brought high after t rch time at the end of the software reset instruction and requires t rst time before executing the next instruction af ter the software reset. see figure 4.13, software reset input timing on page 29 note : the t rch is a cypress specific parameter and cs# must be brought high after t rch time, if not the software reset will not be executed. figure 8.22 software reset command sequence 8.4.1 software reset enable (66h) the reset enable (66h) command is required immediately before a software reset command (99h) such that a software reset is a sequence of the two commands. any command other than reset (99h) following the reset enable (66h) command, will clear the reset enable condition and prevent a la ter rst command from being recognized. 8.4.2 software reset (99h) the reset (99h) command immediately following a reset enable (66h) command, initiates the software reset process. any command other than reset (99h) following the reset enable (66h ) command, will clear the reset enable condition and prevent a later reset (99h) command from being recognized. 8.4.3 continuous read m ode reset ( ffh or ffffh) the ?continuous read mode? bits are used in conjunction with ?fast read dual i/o? and ?fast read quad i/o? commands to provide the highest random flash memory access rate with minimum spi instruction overhead, thus allowing more efficient xip (execute in place) with this device family. a device that is in a continuous high performance read mode may not recognize any normal spi command or the software re set command may not be recognized by the device. it is recommended to use the continuous read mode reset command af ter a system power on reset or, before sending a software reset, to ensure the device is released fr om continuous high performance read mode. cs# sck io0 io1 io2 io3 phase 7 6 5 4 3 2 1 0 .x .x .x .x .x .x w4 .x .x .x .x .x .x .x w5 .x .x .x .x .x .x .x w6 .x .x .x .x .x .x .x .x .x instruction don?t care wrap cs# sck si so phase 7 6 5 4 3 2 1 0 instruction
document number: 002-00497 rev. *e page 77 of 90 s25FL116K, s25fl132k, s25fl164k the ?continuous read mode? bits m7-0 are set by the dual/quad i/ o read commands. m5-4 are used to control whether the 8-bit spi instruction code (bbh or ebh) is neede d or not for the next command. when m5-4 = (1,0), the next command will be treated th e same as the current dual/quad i/o read command without needing t he 8-bit instruction code; when m5-4 do not equal to (1,0), the device returns to normal spi command mode, in which all commands can be accepted. m7-6 and m3-0 are reserved bits for future use, either 0 or 1 values can be used. the continuous read mode reset command (ffh or ffffh) can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation, as shown in figure 8.23 . figure 8.23 continuous read mode reset for fast read dual or quad i/o notes: 1. to reset ?continuous read mode? during quad i/o operation, only eight clocks are needed. the instruction is ?ffh?. 2. to reset ?continuous read mode? during dual i/o operation, sixteen clocks are needed to shift in instruction ?ffffh?. 8.4.4 host system reset commands since s25fl1-k does not have a hardware reset pin, if the host system memory controller resets , without a complete power-down and power-up sequence, while an s25fl1-k device is set to cont inuous mode read, the s25fl1- k device will not recognize any initial standard spi commands from the controller. to address this possibility, it is recommended to issue a continuous read mo de reset (ffffh) command as the first command after a system reset. doing so will release the device from the continuous read mode and allow standard spi commands to be recognized. see section 8.4.3, continuous read mode reset (ffh or ffffh) on page 76 . if burst wrap mode is used, it is also recommended to issue a se t burst with wrap (77h) command that sets the w4 bit to one as the second command after a system reset. doing so will release the de vice from the burst wrap mo de and allow standard sequential read spi command operation. see section 8.3.7, set burst with wrap (77h) on page 75 . issuing these commands im mediately after a non-power-cycle (warm) system reset, ensures the device o peration is co nsistent with the power-on default device operation. the same co mmands may also be issued after device power-on (cold) reset so that system reset code is the same for warm or cold reset. 8.5 id and security commands 8.5.1 deep-power-down (b9h) although the standby current during normal o peration is relatively low, standby current can be further reduced with the deep-po wer- down command. the lower power consumption makes the deep -power-down (dpd) command especially useful for battery powered applications (see i cc1 and i cc2 in section 4.8, ac electrical characteristics on page 25 ). the command is initiated by driving the cs# pin low and shifting the instruction code ?b9h? as shown in figure 8.24 . the cs# pin must be driven high after the eighth bit has been latched. if this is not done the deep-power-down command will not be executed. after cs# is driven high, the power-down state will entered within the time duration of t dp ( section 4.8, ac electrical characteristics on page 25 ). while in the power-down state only the release from deep-power-down / device id command, which restores the device to normal operation, will be recognized. all other commands are igno red. this includes the read status regi ster command, which is always available during normal operation. ignor ing all but one command also makes the power down state a useful condition for securing maximum write protection. the de vice always powers-up in the normal operation with the standby current of i cc1 . cs# sck io0 io1 io2 io3 dio_phase qio_phase ffffh optional ffh mode bit reset for quad i/o optional ffh
document number: 002-00497 rev. *e page 78 of 90 s25FL116K, s25fl132k, s25fl164k figure 8.24 deep power-down command sequence 8.5.2 release from deep-pow er-down / device id (abh) the release from deep-power-down / device id command is a mult i-purpose command. it can be used to release the device from the deep-power-down state, or obtain the de vices electronic identif ication (id) number. to release the device from the deep-power- down state, the command is i ssued by driving the cs# pin lo w, shifting the instructio n code ?abh? and driving cs# high as shown in figure 8.25 . release from deep-power-down will take the time duration of t res1 ( section 4.8, ac electrical characteristics on page 25 ) before the device will resume normal operation and other commands are accepted. the cs# pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the deep po wer-down state, the command is in itiated by driving the cs# pin low and shifting the instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of sck with most significant bit (msb) first. the de vice id values for the s25fl1-k is listed in section 6.6.1, legacy device identification commands on page 60 . the device id can be read continuously. the command is completed by driving cs# high. when used to release the device from the deep-power-down state and obtain the device id, the command is the same as previously described, and shown in figure 8.26 , except that after cs# is driven high it must remain high for a time duration of t res2 . after this time duration the device will resume normal operation and other co mmands will be accepted. if the release from deep-power-down / device id command is issued while an erase, program or write cycle is in proc ess (when busy equals 1) the command is ignored and will not have any effects on the current cycle. figure 8.25 release from deep-power-down command sequence figure 8.26 read electronic signature (res abh) command sequence cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7 6 5 4 3 2 1 0 instruction cs# sck si so phase 7654321023 10 76543210 instruction (abh) dummy device id
document number: 002-00497 rev. *e page 79 of 90 s25FL116K, s25fl132k, s25fl164k 8.5.3 read manufacturer / device id (90h) the read manufacturer / device id command is an alternative to the release from deep-power-down / device id command that provides both the jedec assigned manufac turer id and the specific device id. the read manufacturer / device id command is very similar to the release from deep-power-down / device id command. the command is initiated by driving the cs# pin low and shifting t he instruction code ?90h? followed by a 24-bit address (a23-a0) o f 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of sck with most significant bi t (msb) first as shown in figure 8.27 . the device id values for the s25fl1-k is listed in section 6.6.1, legacy device identification commands on page 60 . if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read co ntinuously, alternating from one to the other. the command is completed by driving cs# high. figure 8.27 read_id (90h) command sequence 8.5.4 read jedec id (9fh) for compatibility reasons, the s25fl1-k provides several commands to electronically determine the identity of the device. the r ead jedec id command is compatible with the jedec standard for spi compatible serial flash memories that was adopted in 2003. the command is initiated by driving the cs # pin low and shifting the instruction code ?9fh?. the jedec assigned manufacturer id byte and two device id bytes, memory type (id15-id8) and capac ity (id7-id0) are then shifted out on the falling edge of sck wit h most significant bit (msb) first as shown in figure 8.28 . for memory type and capacity values refer to section 6.6.1, legacy device identification commands on page 60 . figure 8.28 read jedec id command sequence 8.5.5 read sfdp register / r ead unique id number (5ah) the read sfdp command is initiated by driving the cs# pin low and shifting the instruction code ?5ah? followed by a 24-bit addr ess (a23-a0) into the si pin. eight ?dummy? clocks are also required before the sfdp register contents are shifted out on the falli ng edge of the 40th sck with most signifi cant bit (msb) first as shown in figure 8.29 . for sfdp register values and descriptions, refer to table 6.6.2, serial flash discoverable parameters (sfdp) on page 60 . note: a23-a8 = 0; a7-a0 are used to define the starting byte address fo r the 256-byte sfdp register. the 5ah command can also be used to access the read unique id nu mber. this is a factory-set read-only 8-byte number that is unique to each s25fl1-k device. the id number can be used in co njunction with user software meth ods to help prevent copying or cloning of a system. cs# sck si so phase 7654321023 10 7654321076543 210 instruction (90h) address manufacturer id device id cs# sck si so phase 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction data 1 data n
document number: 002-00497 rev. *e page 80 of 90 s25FL116K, s25fl132k, s25fl164k figure 8.29 read sfdp register command sequence 8.5.6 erase security registers (44h) the erase security register command is similar to the sector erase command. a write enable command must be executed before the device will accept the erase security register command (statu s register bit wel must equal 1). the command is initiated by driving the cs# pin low and shifting the instruction code ?44h? fo llowed by a 24-bit address (a23-a0) to erase one of the secur ity registers. note: 1. addresses outside the ranges in the table have undefined results. the erase security register command sequence is shown in figure 8.30 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the command will not be executed. after cs# is dr iven high, the self-timed eras e security register operation will commence for a time duration of t se (see section 4.8, ac electrical characteristics on page 25 ). while the erase security register cycle is in progress, the read status register command may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other commands again. afte r the erase security register cycle has fini shed the write enable latch (wel) bit in the status register is cleared to 0. the secu rity register lock bits (lb3:1) in the stat us register-2 can be used to otp protect th e security registers. once a lock bit is set to 1, the correspond ing security register will be pe rmanently locked, and an erase s ecurity register command to that register will be ignored (see security register lock bits (lb3, lb2, lb1, lb0) on page 57 ). figure 8.30 erase security registers command sequence 8.5.7 program security registers (42h) the program security register command is similar to the page progr am command. it allows from one byte to 256 bytes of security register data to be programmed at previously erased (ffh) me mory locations. a write enable command must be executed before the device will accept the program security register command (s tatus register bit wel= 1). the command is initiated by driving the cs# pin low then shifting t he instruction code ?42h? followed by a 24-bit address (a23-a0) and at least one data byte, into the si pin. the cs# pin must be held low for the entire length of the command while data is being sent to the device. address a23-16 a15-8 a7-0 security register-1 00h 10h xxh security register-2 00h 20h xxh security register-3 00h 30h xxh cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1 cs# sck si so phase 76 54321023 1 0 instruction address
document number: 002-00497 rev. *e page 81 of 90 s25FL116K, s25fl132k, s25fl164k note: 1. addresses outside the ranges in the table have undefined results. the program security register command sequence is shown in figure 8.31 . the security register lock bits (lb3:1) in the status register-2 can be used to otp protect the se curity registers. once a lock bit is se t to 1, the corresponding security register will be permanently locked, and a program security register command to that register will be ignored (see security register lock bits (lb3, lb2, lb1, lb0) on page 57 and page program (02h) on page 68 for detail descriptions). figure 8.31 program security registers command sequence 8.5.8 read security registers (48h) the read security register command is similar to the fast r ead command and allows one or more data bytes to be sequentially read from one of the three security regi sters. the command is initia ted by driving the cs# pin lo w and then shifting the instru ction code ?48h? followed by a 24-bit address (a 23-a0) and eight ?dummy? clocks into the si pin. the code and address bits are latche d on the rising edge of the sck pin. after the address is received, and following the eight dummy cycles , the data byte of the addressed memory location will be shifted out on the so pin at the falling edge of sck with most significant bit (msb) first. l ocations with address bits a23-a16 not equal to zero, have undefined data . the byte address is automatic ally incremented to the next byt e address after each byte of data is shifted out. once the byte address reaches the last byte of the register (byte ffh), it will reset to 00h, the first byte of the register, and continue to increment. the command is completed by driving cs# high. the read security register command sequence is shown in figure 8.32 . if a read security register command is issued while an erase, program, or write cycle is in process (busy=1), the comm and is ignored an d will not have any effects on the current cycle. the read securit y register command allows clock rates from dc to a maximum of f r (see section 4.8, ac electrical characteristics on page 25 ). note: 1. addresses outside the ranges in the table have undefined results. figure 8.32 read security registers command sequence address a23-16 a15-8 a7-0 security register-1 00h 10h byte address security register-2 00h 20h byte address security register-3 00h 30h byte address address a23-16 a15-8 a7-0 security register-0 (sfdp) 00h 00h byte address security register-1 00h 10h byte address security register-2 00h 20h byte address security register-3 00h 30h byte address cs# sck si so phase 7 6 5 4 3 2 1 0 23 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 instruction address input data 1 input data 2 cs# sck si so phase 7 6 5 4 3 2 1 0 23 1 0 7 6 5 4 3 2 1 0 instruction address dummy cycles data 1
document number: 002-00497 rev. *e page 82 of 90 s25FL116K, s25fl132k, s25fl164k 8.6 set block / pointer protecti on (39h) ? s25fl 132k and s25fl164k the user has a choice to enable one of two protection mechanisms: block protection or pointer pr otection. only one protection mechanism can be enabled at one time. the set block / pointer protection (39h) is a new command (see figure 8.33 ) and is used to determine which one of the two protection mechanisms is enabled, and if the pointer protection mechanism is enabled, determines the pointer address. the write enable command must precede the set block / pointer command. after the set block / pointer protection command is given, the val ue of a10 in byte 3 selects whether the block protection or t he pointer protection mechanism will be enabled. if a10 = 1, then t he block protection mode is enabled. this is the default state, and the rest of pointer values are don?t care. if a10=0, then the poin ter protection is enabled, and th e block protection feature is di sabled. the pointer address values a9 to a0 are don?t care. if the pointer protection mechanism is enabled, a pointer ad dress determines the boundary be tween the protected and the unprotected regions in the memory. the form at of the set pointer command is the 39h instruction followed by three address bytes . for the s25fl132k, ten address bits (a21-a12) after the 39h comm and are used to program the non-volatile pointer address. for the 32m, a23 ? a22 are don?t care. for the s25fl164k, eleven add ress bits (a22-a12) after the 39h command are used to program the non-volatile pointer address. for the 64m, a23 is a don?t care. the a11 bit can be used to protect all sector s. if a11=1, then all sectors are protecte d, and a23 ? a12 are don?t cares. if a11 =0, then the unprotected range will be determined by a22-a12 for the 64m and a21-a12 for the 32m. the area that is unprotected will be inclusive of the 4-kb sector selected by the pointer address. bit 5 (top / bottom) of sr1 is used to determine whether the regi on that will be unprotected will start from the top (highest a ddress) or bottom (lowest address) of the memory array to the location of the pointer. if tb=0 and the 39h command is issued followed b y a 24-bit address, then the 4-kb sector whic h includes that address and all the sector s from the bottom up (zero to higher address ) will be unprotected. if tb=1 and 39h command is issued followed by a 24-bit address then the 4-kb sect or which includes that address and all the sectors from the top down (max to lower address) will be unprotected. the srp1 (sr2 [0]) and srp0 (sr1 [7]) bits are used to protect the pointer address in the same way they protect sr1 and sr2. when srp1 and srp0 protect sr1 and sr2, the 39h command is i gnored. this effectively prevents changes to the protection scheme using the existing srp1-srp0 mechanism ? including the otp protection option. the 39h command is ignored during a suspend operation because the pointer address cannot be erased and re-programmed during a suspend. the read status register-3 command 33h (see figure 8.2 for 33h timing diagram) reads the contents of sr3 followed by the contents of the pointer. this allows the contents of the poin ter to be read out for test and verification. the read back order is sr3, a23-a16, a15-a8. if cs# remains low, the bytes after a15-a8 are undefined. notes: 1. amax = 7fffffh for the fl164k, and 3fffffh for the fl132k. 2. a<21-12> for the fl132k. tb a11 a10 protect address range unprotect address range comment xx1 see block protect method see block protect method a10 = 1 the block protect protec tion mode is enabled (this is the default state and the rest of pointer address is don't care). 000 amax (1) to (a<22-12>+1) a<22-12> (2) to 000000 if tb=0 and the 39h command is issued followed by a 24-bit address, then the 4-kb sector which includes that address and all the sectors from the bottom up (zero to higher address) will be unprotected. 100 (a<22-12>-1) to 000000 amax (1) to a<22-12> if tb=1 and 39h command is issued followed by a 24-bit address then the 4-kb sector wh ich includes that address and all the sectors from the top down (max to lower address) will be unprotected. x10 amax (1) to 000000 not applicable a10=0 and a11 =1 means protect all sectors and amax-a12 are don't care.
document number: 002-00497 rev. *e page 83 of 90 s25FL116K, s25fl132k, s25fl164k block erase: in general, if the pointer protect scheme is active (a10=0), protect all sectors is not active (a11=0), and the po inter address points to anywhere within the block, the whole block will be protected from bloc k erase even though part of the block i s unprotected. the 2 exceptions where block erase goes through is if the pointer address points to the top sector of the block(a[15:12]=1111) if tb=0, and if t he pointer points to the bottom sector of the block (a[15:12]=0000) and tb=1. figure 8.33 set pointer address (39h) cs# sck si so phase 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 x x x x x x x x x x instruction address dummy cycles
document number: 002-00497 rev. *e page 84 of 90 s25FL116K, s25fl132k, s25fl164k 9. data integrity 9.1 erase endurance note: 1. each write command to a non-volatile register causes a pe cycl e on the entire non-volatile register array. otp bits and regis ters internally reside in a separate array that is not cycled. 9.2 data retention 9.3 initial delivery state the device is shipped from cypress with non-vol atile bits / default states set as follows: ? the entire memory array is erased: i.e. all bits are set to 1 (each byte contains ffh). ? the unique device id is programmed to a random number seeded by the date and time of device test. ? the sfdp security register address space 0 contains the values as defined in table 6.6.2, serial flash discoverable parameters (sfdp) on page 60 . security register address spaces 1 to 3 are erased: i.e. all bits are set to 1 (each byte contains ffh). ? status register-1 contains 00h. ? status register-2 contains 04h. ? status register-3 contains 70h. table 9.1 erase endurance parameter min unit program/erase cycles main flas h array sector 100k pe cycle program/erase cycles security regi sters non-volatile register array (1) 1k pe cycle parameter test conditions minimum time unit data retention time main flash array 10k program/erase cycles @ 55c 20 years data retention time main flash array 100k program/erase cycles @ 55c 2 years data retention time security registers non-volatile re gister array 1k program/erase cycles @ 55c 20 years
document number: 002-00497 rev. *e page 85 of 90 s25FL116K, s25fl132k, s25fl164k 10. ordering information the ordering part number is formed by a valid combination of the following: s25fl1 32 k 0x m f i 01 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 00 = 16-lead so package (300 mil) 01 = 8-lead so package (208 mil) / 8-contact wson 02 = 5 x 5 ball bga package 03 = 4 x 6 ball bga package (208 mil) 04 = 8-lead so package (150 mil) / 8-contact uson (4 mm ? 4 mm) q1 = 8-lead so package (208 mil) / 8-contact wson (default quad mode enabled) temperature range a = industrial, gt grade, aec-q100 grade 3 (-40c to +85c) b = industrial plus, gt grade, aec-q100 grade 2 (-40c to +105c) m = extended, gt grade, aec-q100 grade 1 (-40c to +125c) i = industrial (-40c to +85c) v = industrial plus (-40c to +105c) n = extended (-40c to +125c) package materials f =lead (pb)-free, halogen-free h= low-halogen, lead (pb)-free package type m = 8-lead / 16-lead so package n = 8-contact wson/uson package b = 24-ball 6 ? 8 mm bga package, 1.0 mm pitch speed 0x = 108 mhz device technology k = 90 nm floating gate process technology density 16 = 16 mbits 32 = 32 mbits 64 = 64 mbits device family s25fl1 cypress memory 3.0 volt-only, serial peripheral interface (spi) flash memory
document number: 002-00497 rev. *e page 86 of 90 s25FL116K, s25fl132k, s25fl164k valid combinations ? standard table 10.1 lists standard configurations planned to be supported in volume for this device. co nsult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. note: 1. contact the factory for extended (-40c to +125c) temperature range opn offering. table 10.1 valid combinations for standard part numbers base ordering part number speed option package and temperature model number packing type package marking FL116K 0x mfi 01 0, 1, 3 FL116Kif01 q1 FL116Kifq1 04 FL116Kif4 mfv 01 FL116Kvf01 04 FL116Kvf4 nfi 01 FL116Kif01 q1 FL116Kifq1 nfv 01 FL116Kvf01 bhi 02 0, 3 FL116Kih02 03 FL116Kih03 bhv 02 FL116Kvh02 03 FL116Kvh03 fl132k 0x mfi 01 0, 1, 3 fl132kif01 04 fl132kif4 q1 fl132kifq1 mfv 01 fl132kvf01 04 fl132kvf4 nfi 01 fl132kif01 04 fl132kif04 q1 fl132kifq1 nfv 01 fl132kvf01 04 fl132kvf04 bhi 02 0, 3 fl132kih02 03 fl132kih03 bhv 02 fl132kvh02 03 fl132kvh03 fl164k 0x mfi 00 0, 1, 3 fl164kif00 01 fl164kif01 q1 fl164kifq1 mfv 00 fl164kvf00 01 fl164kvf01 nfi 01 fl164kif01 q1 fl164kifq1 nfv 01 fl164kvf01 bhi 02 0, 3 fl164kih02 03 fl164kih03 bhv 02 fl164kvh02 03 fl164kvh03
document number: 002-00497 rev. *e page 87 of 90 s25FL116K, s25fl132k, s25fl164k valid combinations ? gt grade / aec-q100 table 10.2 lists configurations that are gt grade / aec-q100 qualified and are planned to be available in volume. consult your local sales office to confirm availability of specific valid co mbinations and to check on newly released combinations. gt grade is the cypress quality and reliability rating to indica te products that are intended for high reliability applications such as automotive. qualification according to aec-q100 is a prerequisite for all gt grade products. table 10.2 valid combinations for gt grade part numbers base ordering part number speed option package and temperature model number packing type package marking FL116K 0x mfa 01 0, 1, 3 FL116Kaf01 q1 FL116Kafq1 04 FL116Kaf4 mfb 01 FL116Kbf01 04 FL116Kbf4 nfa 01 FL116Kaf01 q1 FL116Kafq1 nfb 01 FL116Kbf01 bha 02 0, 3 FL116Kah02 03 FL116Kah03 bhb 02 FL116Kbh02 03 FL116Kbh03 fl132k 0x mfi 01 0, 1, 3 fl132kaf01 q1 fl132kafq1 04 fl132kaf4 mfb 01 fl132kbf01 04 fl132kbf4 nfa 01 fl132kaf01 04 fl132kaf04 q1 fl132kafq1 nfb 01 fl132kbf01 04 fl132kbf04 bha 02 0, 3 fl132kah02 03 fl132kah03 bhb 02 fl132kbh02 03 fl132kbh03
document number: 002-00497 rev. *e page 88 of 90 s25FL116K, s25fl132k, s25fl164k fl164k 0x mfi 01 0, 1, 3 fl164kaf01 q1 fl164kafq1 00 fl164kaf00 mfb q1 fl164kafq1 mfv 01 fl164kbf01 00 fl164kbf00 nfi 01 fl164kaf01 q1 fl164kafq1 nfv 01 fl164kbf01 bha 02 0, 3 fl164kah02 03 fl164kah03 bhb 02 fl164kbh02 03 fl164kbh03 table 10.2 valid combinations for gt grade part numbers (continued) base ordering part number speed option package and temperature model number packing type package marking
document number: 002-00497 rev. *e page 89 of 90 s25FL116K, s25fl132k, s25fl164k 11. revision history document history page document title: s25FL116K, s25fl132k, s25fl164k 16 mbit (2 mb yte), 32 mbit (4 mbyte), 64 mbit (8 mbyte) 3.0v spi flash memory document number: 002-00497 rev. ecn no. orig. of change submission date description of change ** ? bwha 04/14/2014 initial release combined s25FL116K_00_06 and s25fl132k_164k_00_05 global: promoted data sheet from pr eliminary to full production added 125c option *a ? bwha 10/10/2014 migration notes: fl generations comparison ta ble: corrected sector erase time (typ.) for s25fl1-k ac electrical characte ristics: ac electrical characteristics ? -40c to +85c/105c at 2.7v to 3.6v table: added trch and trst input / output timing: added software reset input timing figure physical interface: corrected figure: 8-contact wson (5 mm x 6 mm) package security register 0 ? serial flash discoverable parameters (sfdp ? jedec jesd216b): updated section based on revised jedec jesd216b spec commands: added command set (reset commands) table reset commands: added sections: reset commands, software reset enable (66h), software reset (99h) updated section: continuous read mode reset (ffh or ffffh) *b ? bwha 12/04/2014 power-up timing: power-up timing and voltage levels table: corrected tpuw valid combinations: valid combinations t able: corrected FL116K model number and package marking *c 4891479 bwha 09/18/2015 updated to cypress template *d 5044503 bwha 12/18/2015 updated package options in features . added uson 4 mm ? 4 mm package. updated figure 5.1 through figure 5.5 . added unf008 ? 8-contact uson 4 mm x 4 mm . updated ordering information : added halogen-free description to so packages. added gt grade ordering information. *e 5270099 bwha 06/29/2016 added logic block diagram . added thermal resistance section. added data retention section. updated table 10.2 .
document number: 002-00497 rev. *e revised june 29, 2016 page 90 of 90 s25FL116K, s25fl132k, s25fl164k ? cypress semiconductor corporation, 2014-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a crit ical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | projects | video | blogs | training | components technical support cypress.com/support

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